Datasheet
THEORY OF OPERATION
GENERAL DESCRIPTION
R
2R
2R2R 2R 2R 2R 2R 2R 2R
V -F
REFH
V -F
REFL
V
OUT
R
FB
V
REFH
V -S
REFH
V -S
REFL
R
FB
(1)
5kW
5kW
NOTE:(1) R =5kW forgain=1
FB
R =10kW forg ia n = 2.
FB
DAC9881
SBAS438A – MAY 2008 – REVISED AUGUST 2008 .........................................................................................................................................................
www.ti.com
The DAC9881 is a single-channel, 18-bit, serial-input, voltage-output digital-to-analog converter (DAC). The
architecture is an R-2R ladder configuration with the four MSBs segmented, followed by an operational amplifier
that serves as a buffer, as shown in Figure 64 . The on-chip output buffer allows rail-to-rail output swings while
providing a low output impedance to drive loads. The DAC9881 operates from a single analog power supply that
ranges from 2.7V to 5.5V, and typically consumes 850 µ A when operating with a 5V supply. Data are written to
the device in a 24-bit word format, via an SPI serial interface. To enable compatibility with 1.8V, 3V, or 5V logic
families, an IOV
DD
supply pin is provided. This pin allows the DAC9881 input and output logic to be powered
from the same logic supply used to interface signals to and from the device. Internal voltage translators are
included in the DAC9881 to interface digital signals to the device core. See Figure 65 for the basic configuration
of the DAC9881.
To ensure a known power-up state, the DAC9881 is designed with a power-on reset function. Upon power-up,
the DAC9881 is reset to either zero-scale or midscale depending on the state of the RSTSEL pin. A harrdware
reset can be performed by using the RST and RSTSEL pins.
Figure 64. DAC9881 Architecture
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Product Folder Link(s): DAC9881