Datasheet

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.54.0 5.0
LogicInputVoltage(V)
200
180
160
140
120
100
80
60
40
20
0
IOV SupplyCurrent( A)m
DD
IOV =5V
DD
IOV =2.7V
DD
Time(2 s/div)m
2V/div 1mV/div
5V/div
Large-SignalOutput
LDAC
Signal
CodeChange:00000hto3FFFFh
OutputLoadedwith10k andW
50pFtoAGND
Small-SignalError
Time(2 s/div)m
2V/div
1mV/div
5V/div
Large-
Signal
Output
LDAC
Signal
CodeChange:3FFFFhto00000h
OutputLoadedwith10k andW
50pFtoAGND
Small-SignalError
Time(2 s/div)m
2V/div
1mV/div
5V/div
Large-SignalOutput
LDAC
Signal
CodeChange:04000hto3C000h
OutputLoadedwith10k andW
50pFtoAGND
Small-SignalError
Time(2 s/div)m
2V/div
1mV/div
5V/div
Large-SignalOutput
LDAC
Signal
CodeChange:3C000hto04000h
OutputLoadedwith10k andW
50pFtoAGND
Small-SignalError
DAC9881
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......................................................................................................................................................... SBAS438A MAY 2008 REVISED AUGUST 2008
TYPICAL CHARACTERISTICS: AV
DD
= +5V (continued)
At T
A
= +25 ° C, V
REFH
= +5.0V, V
REFL
= 0V, and Gain = 1X Mode, unless otherwise noted.
OUTPUT VOLTAGE
vs DRIVE CURRENT CAPABILITY IOV
DD
SUPPLY CURRENT
(Operation Near AGND Rail) vs LOGIC INPUT VOLTAGE
Figure 28. Figure 29.
LARGE SIGNAL LARGE SIGNAL
SETTLING TIME SETTLING TIME
Figure 30. Figure 31.
LARGE SIGNAL LARGE SIGNAL
SETTLING TIME SETTLING TIME
Figure 32. Figure 33.
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