Datasheet

CS
Case1: DaisyChain, tiedlow.LDAC
Case2: DaisyChain, active.LDAC
SCLK
SDI
SDO
LDAC
t
9
t
8
t
4
t
5
t
6
t
3
t
1
t
2
t
7
InputRegister
andDACLatch
Updated
High-Z
Low
High-Z
Bit23(N)
(1)
Bit0(N)
Bit23(N) Bit22(N) Bit23(N+1) Bit0(N+1)Bit0(N)
t
11
t
13
t
12
t
10
=Don’tCare
Bit23=MSB
Bit0=LSB
CS
SCLK
SDI
SDO
LDAC
t
9
t
8
t
4
t
5
t
6
t
3
t
1
t
2
t
7
High-Z High-Z
Bit23(N)
(1)
Bit0(N)
Bit23(N) Bit22(N) Bit23(N+1) Bit0(N+1)Bit0(N)
t
11
t
13
t
12
t
10
InputRegister
Updated
High
DACLatch
Updated
t
14
t
15
NOTE:(1)SDOdatadelayedfromSDIby24clockcycles.
DAC9881
www.ti.com ......................................................................................................................................................... SBAS438A – MAY 2008 – REVISED AUGUST 2008
Figure 3. Timing Diagram for Daisy Chain Mode, Two Cascaded Devices
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