Datasheet

EVM Operation www.ti.com
5.3.2 SDI Signal
The SDI signal is the serial data input that is loaded into the DAC’s input register. The data frame sent to
the DAC9881 is 24-bits wide. The first 6 bits are 'don't care', the seventh bit is the most-significant bit
(MSB) of the DAC data and the 24th bit is the least significant bit (LSB) of the 18-bit DAC data. The serial
data input is driven from the SPI master on the falling SCLK edge and sampled by the DAC9881 on the
rising edge of the serial clock.
5.3.3 SCLK Signal
The host processor must provide an SCLK signal which is used to advance serial data through the DAC’s
serial shift register. The serial clock rate can operate at speeds up to 50 MHz. The 6 don't care bits plus
18-bit data is shifted out of the bus master synchronously on the falling edge of SCLK and latched on the
rising edge of SCLK into the DAC’s serial shift register. After 24-bits are transferred or 24 SCLK cycles are
generated, the bus master must take the CS signal high. If the CS signal is held low and more than 24
SCLK cycles are applied, the last SCLK cycle is considered the least significant bit (LSB) of the 18-bit
data stream loaded into the DAC’s serial shift register.
5.3.4 LDAC Signal
The LDAC signal is a control input signal that can be used to update the DAC output at a specific point in
time. This signal is active low and can be triggered synchronously or asynchronously. If LDAC is held low,
the DAC9881 output updates with the rising edge of the CS input. If multiple DAC9881 devices share the
databus in daisy-chain fashion, a common LDAC signal can be used to update multiple DAC outputs
simultaneously.
5.3.5 RST Signal
The RST signal is the control input used to reset the DAC output to a known state which is determined by
the logic level of the RSTSEL pin when the RST pin is asserted. If RSTSEL is tied to DGND, the DAC
output latch is cleared (0 V) and V
OUT
is minimum scale (i.e., V
REF
L). If RSTSEL is tied to VDD, the DAC
output latch is set to midscale and V
OUT
is equal to (V
REF
H – V
REF
L)/2. This pin is an active low input.
5.3.6 PDN Signal
The PDN signal is the control input provided for hardware power-down function of the device. This signal
is active high, so when the PDN pin is driven high, the device goes into power-down mode, which reduces
its power consumption. The DAC9881 voltage output pin is connected to ground through an internal 10-kΩ
resistor while in power-down mode.
5.4 Analog Output
The DAC9881 voltage output is buffered internally and offers a force and sense output configuration to
allow the loop around the output amplifier to be closed as near to the load as possible. The EVM closes
this loop by default with R1 installed, so if the loop at the load needs to be closed, R1 must be removed
and jumpers W2 and W7 used to connect V
OUT
and R
FB
to the connector J4. The selected pins of the J4
connector, as dictated by the jumper positions of W2 and W7 jumpers, can then be connected to the load
to close the loop.
The EVM includes an external operational amplifier, U2, as an option for other output signal-conditioning
circuitry for the DAC output. Although the buffered output of the DAC9881 can be monitored through J4
pin 2, the optional external buffer output (if the DAC output is connected to it) can be monitored through
the TP3 test point.
The external operational amplifier, U2, is set to unity gain configuration by default to maintain the
DAC9881 unipolar output mode of operation. But it can be modified by simple jumper settings to achieve
other modes of operation. The following sections describe the different configurations of the output
amplifier, U2.
12
DAC9881 Evaluation Module SLAU279A–March 2009–Revised November 2009
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