Datasheet

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5.2 Host Processor Interface
The DAC9881 supports high-speed serial peripheral interface (SPI) to communicate with gate arrays,
microprocessors or DSP devices. The user supplied host processor drives the serial communication to the
DAC9881EVM. The DAC9881EVM provides the necessary connections to the host processor through
connector P2 (located on the bottom side of the board). Proper operation of the DAC9881 depends on the
successful communication between the host processor and the EVM. Communication is based on an SPI
where CPOL = 0 and CPHA = 0. This means the serial clock dwells low in its inactive state and the input
data considered valid on the rising edge of the serial clock.
The following sections describe the basic operation of the digital control inputs to the DAC9881. For more
detailed information regarding the DAC9881 digital interface, see the data sheet (SBAS438).
5.3 Digital Control Interface
The DAC9881 can be considered a 3-wire SPI slave device. The host processor must provide a chip
select ( CS ), the serial data input (SDI) and the serial clock (SCLK) necessary to control the operation of
the DAC9881. A fourth control line called load dac (LDAC) can be used to control the point in time at
which the DAC output data is updated. This is useful in applications where multiple DAC9881's need to be
updated simultaneously. With the exception of the serial data input (SDI) and the serial data output (SDO)
to and from the DAC9881, the EVM incorporates a pass-through connector arrangement to accommodate
the digital control interface of the DAC9881 device via J2 (top side) or P2 (bottom side) connectors. The
signals on these pass-through connectors are listed as shown in Table 3.
Table 3. Digital Control Interface Signal Mapping for J2/P2 Connectors
Pin Number Signal Function
J2.1/P2.1 CS Primary synchronization and device enable input for the DAC9881. Host microcontroller’s STE signal for
SPI interface.
J2.3/P2.3 SCLK Serial interface clock.
J2.5/P2.5 CLKR Unused.
J2.7/P2.7 FS Secondary synchronization and device enable input for the DAC9881. Host microcontroller’s STE signal
for SPI interface or FS signal from DSP host system.
J2.9/P2/9 FSR Unused.
J2.11 SDO Serial Data Output.
P2.11 SDI Serial Data Input.
J2.13/P2.13 DR Unused.
J2.15/P2.15 LDAC1 GPIO signal to control LDAC for DAC output latch update.
J2.17/P2.17 LDAC2 Alternate GPIO signal to control LDAC for DAC output latch update.
J2.19/P2.19 RST GPIO signal to control RST for DAC reset function.
J2.2/P2.2 PDN GPIO signal to control PDN for hardware power down.
J2.4/P2.4 GND Signal Ground
J2.10/P2.10
J2.18/P2.18
J2.6/P2.6 GPIOs Unused
J2.8/P2.8
J2.12/P2.12
J2.14/P2.14
J2.16/P2.16
J2.20/P2.20
5.3.1 CS Signal
The signals found on J2 pins 1 and 7 of the EVM are used to control the chip select input of the DAC9881.
These signals are configurable via wire jumper W6. Either signal can be chosen to drive the DAC9881 CS
pin. The basic function of the CS input signal is to enable serial communication with the DAC9881. This
signal must be held low while the host processor is accessing the DAC serial shift register. The
low-to-high transition of this signal transfers the content of the serial shift register to the DAC input
register. The CS input can also be used to update the DAC output if the LDAC is tied to ground.
11
SLAU279A–March 2009–Revised November 2009 DAC9881 Evaluation Module
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