Datasheet

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TIMING CHARACTERISTICS for Figure 1
(1) (2) (3)
DAC8881
SBAS422A JULY 2007 REVISED SEPTEMBER 2007
At 40 ° C to +105 ° C, unless otherwise noted.
PARAMETER CONDITIONS MIN MAX UNIT
2.7 DV
DD
< 3.6V, 2.7 IOV
DD
DV
DD
40 MHz
f
SCLK
Maximum clock frequency
3.6 DV
DD
5.5V, 2.7 IOV
DD
DV
DD
50 MHz
2.7 DV
DD
< 3.6V, 2.7 IOV
DD
DV
DD
50 ns
t
1
Minumum CS high time
3.6 DV
DD
5.5V, 2.7 IOV
DD
DV
DD
30 ns
2.7 DV
DD
< 3.6V, 2.7 IOV
DD
DV
DD
10 ns
t
2
CS falling edge to SCLK rising edge
3.6 DV
DD
5.5V, 2.7 IOV
DD
DV
DD
8 ns
2.7 DV
DD
< 3.6V, 2.7 IOV
DD
DV
DD
10 ns
SCLK falling edge to CS falling edge setup
t
3
time
3.6 DV
DD
5.5V, 2.7 IOV
DD
DV
DD
10 ns
2.7 DV
DD
< 3.6V, 2.7 IOV
DD
DV
DD
10 ns
t
4
SCLK low time
3.6 DV
DD
5.5V, 2.7 IOV
DD
DV
DD
10 ns
2.7 DV
DD
< 3.6V, 2.7 IOV
DD
DV
DD
15 ns
t
5
SCLK high time
3.6 DV
DD
5.5V, 2.7 IOV
DD
DV
DD
10 ns
2.7 DV
DD
< 3.6V, 2.7 IOV
DD
DV
DD
25 ns
t
6
SCLK cycle time
3.6 DV
DD
5.5V, 2.7 IOV
DD
DV
DD
20 ns
2.7 DV
DD
< 3.6V, 2.7 IOV
DD
DV
DD
10 ns
t
7
SCLK rising edge to CS rising edge
3.6 DV
DD
5.5V, 2.7 IOV
DD
DV
DD
10 ns
2.7 DV
DD
< 3.6V, 2.7 IOV
DD
DV
DD
8 ns
t
8
Input data setup time
3.6 DV
DD
5.5V, 2.7 IOV
DD
DV
DD
5 ns
2.7 DV
DD
< 3.6V, 2.7 IOV
DD
DV
DD
5 ns
t
9
Input data hold time
3.6 DV
DD
5.5V, 2.7 IOV
DD
DV
DD
5 ns
2.7 DV
DD
< 3.6V, 2.7 IOV
DD
DV
DD
10 ns
t
14
CS rising edge to LDAC falling edge
3.6 DV
DD
5.5V, 2.7 IOV
DD
DV
DD
5 ns
2.7 DV
DD
< 3.6V, 2.7 IOV
DD
DV
DD
15 ns
t
15
LDAC pulse width
3.6 DV
DD
5.5V, 2.7 IOV
DD
DV
DD
10 ns
(1) All input signals are specified with t
R
= t
F
= 2ns (10% to 90% of IOV
DD
) and timed from a voltage level of IOV
DD
/2.
(2) Ensured by design. Not production tested.
(3) Sample tested during the initial release and after any redesign or process changes that may affect these parameters.
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