Datasheet

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TIMING DIAGRAMS
CS
Case1:StandaloneoperationwithoutSDO, tiedlow.LDAC
Case2:StandaloneoperationwithoutSDO, active.LDAC
SCLK
SDI
LDAC
t
9
t
8
t
4
t
5
t
6
t
3
t
1
t
2
t
7
InputRegister
andDACLatch
Updated
Low
Bit15(N) Bit14(N) Bit1(N) Bit0(N)
CS
SCLK
SDI
LDAC
t
9
t
8
t
4
t
5
t
6
t
3
t
1
t
2
t
7
InputRegister
Updated
High
=DontCare
Bit15=MSB
Bit0=LSB
Bit15(N) Bit14(N) Bit1(N) Bit0(N)
DACLatch
Updated
t
14
t
15
DAC8881
SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007
Figure 1. Timing Diagram of Standalone Operation without SDO
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