Datasheet

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PIN CONFIGURATION
SCLK
SDI
LDAC
AGND
AV
DD
V -S
REFL
(ThermalPad)
PDN
RST
USB/BTC
GAIN
RSTSEL
NC
1
2
3
4
5
6
18
17
16
15
14
13
DAC8881
IOV
DD
SDO DGND DV
DD
SDOSEL CS
24 23 22 21 20 19
V -S
REF
H
V
OUT
R
FB
V -F
REFL
V -F
REF
H
NC
7 8 9
10 11 12
DAC8881
SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007
RGE PACKAGE
(1)
QFN-24
(TOP VIEW)
(1) The thermal pad is internally connected to the substrate. This pad can be connected to the analog ground or left
floating. Keep the thermal pad separate from the digital ground, if possible.
TERMINAL FUNCTIONS
TERMINAL
NO. NAME I/O DESCRIPTION
1 SCLK I SPI bus serial clock input
2 SDI I SPI bus serial data input
Load DAC latch control input (active low). When LDAC is low, the DAC latch is transparent, and the contents of the input
3 LDAC I register are transferred to the DAC latch. The DAC output changes to the corresponding level simultaneously when the
DAC latch is updated.
4 AGND I Analog ground
5 AV
DD
I Analog power supply
6 V
REFL
-S I Reference low input sense
7 V
REFH
-S I Reference high input sense
8 V
OUT
O Output of output buffer
9 R
FB
I Feedback resistor connected to the inverting input of the output buffer.
10 V
REFL
-F I Reference low input force
11 V
REFH
-F I Reference high input force
12 NC — Do not connect.
13 NC — Do not connect.
Selects the value of the output from the V
OUT
pin after power-on or hardware reset. If RSTSEL = IOV
DD
, then register data
14 RSTSEL I
= 8000h. If RSTSEL = DGND, then register data = 0000h.
15 GAIN I Buffer gain setting. Gain = 1 when the pin is connected to DGND; Gain = 2 when the pin is connected to IOV
DD
.
Input data format selection. Input data are straight binary format when the pin is connected to IOV
DD
, and in two ’ s
16 USB/ BTC I
complement format when the pin is connected to DGND.
17 RST I Reset input (active low). Logic low on this pin causes the device to perform a reset.
Power-down input (active high). Logic high on this pin forces the device into power-down status. In power-down, the V
OUT
18 PDN I
pin connects to AGND through 10k Ω resistor.
SPI bus chip select input (active low). Data bits are not clocked into the serial shift register unless CS is low. When CS is
19 CS I
high, SDO is in high-impedance status.
SPI serial data output selection. When SDOSEL is tied to IOV
DD
, the contents of the existing input register are shifted out
20 SDOSEL I from the SDO pin; this is Stand-Alone mode. When SDOSEL is tied to DGND, the contents in the SPI input shift register
are shifted out from the SDO pin; this is Daisy-Chain mode for daisy chaining communication.
21 DV
DD
I Digital power supply (connect to AV
DD
, pin 5)
22 DGND I Digital ground
23 SDO O SPI bus serial data output. Refer to the Timing Diagrams for further detail.
24 IOV
DD
I Interface power. Connect to +1.8V for 1.8V logic, +3V for 3V logic, and to +5V for 5V logic.
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): DAC8881