Datasheet

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DOUBLE-BUFFERED INTERFACE

Load DAC Pin ( LDAC)

1.8V TO 5.5V LOGIC INTERFACE

DAC8881

SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007

on the next DAC in the chain, a multi-DAC interface is constructed. 16 clock pulses are required for each DAC in

the system. Therefore, the total number of clock cycles must be equal to (16 x N), where N is the total number of

devices in the chain. When the serial transfer to all devices is complete, CS should be taken high. This action

prevents any further data from being clocked into the input shift register. The contents in the shift registers are

transferred into the relevant input registers on the rising edge of the CS signal.

A continuous SCLK source may be used if CS can be held low for the correct number of clock cycles.

Alternatively, a burst clock containing the exact number of clock cycles can be used and CS can be taken high

some time later. When the transfer to all input registers is complete, a common LDAC signal updates all DAC

registers, and all analog outputs update simultaneously.

The DAC8881 has a double-buffered interface consisting of two register banks: the input register and the DAC

latch. The input register is connected directly to the input shift register and the digital code is transferred to the

input register upon completion of a valid write sequence. The DAC latch contains the digital code used by the

resistor R-2R ladder. The contents of the DAC latch defines the output from the DAC.

Access to the DAC register is controlled by the LDAC pin. When LDAC is high, the DAC register is latched and

the input register can change state without affecting the contents of the DAC latch. When LDAC is low, however,

the DAC latch becomes transparent and the contents of the input register is transferred to the DAC register.

LDAC transfers data from the input register to the DAC register (and, therefore, updates the DAC output). The

contents of the DAC latch (and the output from DAC) can be changed in two ways, depending on the status of

LDAC.

Synchronous Mode

When LDAC is tied low, the DAC register updates as soon as new data are transferred into the input register

after the rising edge of CS.

Asynchronous Mode

When LDAC is high, the DAC latch is latched. The DAC latch (and DAC output) is not updated at the same time

that the input register is written to. When LDAC goes low, the DAC register updates with the contents of the input

All digital input and output pins are compatible with any logic supply voltage between 1.8V and 5.5V. Connect the

interface logic supply voltage to the IOV

pin. Although timing is specified down to 2.7V (see the Timing

Characteristics ), IOV

can operate as low as 1.8V, but with degraded timing and temperature performance. For

the lowest power consumption, logic V

levels should be as close as possible to IOV

, and logic V

levels

should be as close as possible to GND. Note that the DAC8881 core internal digital logic operates from the same

voltage as the 2.7V to 5.5V AV

supply, so the DV

pin must also be connected to the AV

supply voltage.

Product Folder Link(s): DAC8881