Datasheet

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POWER-ON RESET
PROGRAM RESET VALUE
SERIAL INTERFACE
Input Shift Register
DAC8881
SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007
The DAC8881 has a power-on reset function. After power-on, the value of the input register, the DAC latch, and
the output from the V
OUT
pin are set to the value defined by the RSTSEL pin.
After a power-on reset or a hardware reset, the output voltage from the V
OUT
pin and the values of the input
register and DAC latch are determined by the status of the RSTSEL pin and the input data format, as shown in
Table 3 .
Table 3. Reset Value
RSTSEL PIN USB/ BTC PIN INPUT FORMAT V
OUT
VALUE OF INPUT REGISTER AND DAC LATCH
DGND IOV
DD
Straight Binary 0 0000h
IOV
DD
IOV
DD
Straight Binary Midscale 8000h
DGND DGND Two's Complement Midscale 0000h
IOV
DD
DGND Two's Complement 0 8000h
The DAC8881 is controlled by a versatile 3-wire serial interface that operates at clock rates of up to 50MHz and
is compatible with SPI, QSPI™, MICROWIRE™, and DSP™ interface standards.
Data are loaded into the device as a 16-bit word under the control of the serial clock input, SCLK. The timing
diagrams for this operation are shown in the Timing Diagram section.
The CS input is a level-triggered input that acts as a frame synchronization signal and chip enable. Data can be
transferred into the device only while CS is low. To start the serial data transfer, CS should be taken low,
observing the minimum CS falling edge to SCLK rising edge setup time, t
2
. After CS goes low, serial data are
clocked into the device input shift register on the rising edges of SCLK for 16 or more clock pulses. If a frame
contains less than 16 bits of data, the frame is invalid. Invalid data are not written into the input register and
DAC, although the input register and DAC will continue to hold data from the preceding valid data cycle. If more
than 16 bits of data are transmitted in one frame, the last 16 bits are written into the shift register and DAC. CS
may be taken high after the rising edge of the 16th SCLK pulse, observing the minimum SCLK rising edge to CS
rising edge time, t
7
. The contents of the shift register are transferred into the input register on the rising edge of
CS. When data have been transferred into the input register of the DAC, the corresponding DAC register and
DAC output can be updated by taking the LDAC pin low.
Stand-Alone Mode
When the SDOSEL pin is tied to IOV
DD
, the interface is in Stand-Alone mode. This mode provides serial
readback for diagnostic purposes. The new input data (16 bits) are clocked into the device shift register and the
existing data in the input register (16 bits) are shifted out from the SDO pin. If more than 16 SCLKs are clocked
when CS is low, the contents of the input register are shifted out from the SDO pin, followed by zeroes; the last
16 bits of input data remain in the shift register. If less than 16 SCLKs are clocked while CS is low, the data from
the SDO pin are part of the data in the input register and must be ignored. Refer to Figure 2 for further detail.
Daisy-Chain Mode
When the SDOSEL pin is tied to GND, the interface is in Daisy-Chain mode. For systems that contain several
DACs, the SDO pin may be used to daisy-chain several devices together.
In Daisy-Chain mode, SCLK is continuously applied to the input shift register while CS is low. If more than 16
clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. These data are
clocked out on the falling edge of SCLK and are valid on the rising edge. By connecting this line to the DIN input
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