Datasheet

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THEORY OF OPERATION
GENERAL DESCRIPTION
R
2R
2R2R 2R 2R 2R 2R 2R 2R
V -F
REFH
V -F
REFL
V
OUT
R
FB
V
REFH
V -S
REFH
V -S
REFL
R
FB
(1)
5kW
5kW
NOTE:(1) R =5kW forgain=1
FB
R =10kW forg ia n = 2.
FB
DAC8881
SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007
The DAC8881 is a single-channel, 16-bit, serial-input, voltage-output digital-to-analog converter (DAC). The
architecture is an R-2R ladder configuration with the four MSBs segmented, followed by an operational amplifier
that serves as a buffer, as shown in Figure 66 . The on-chip output buffer allows rail-to-rail output swings while
providing a low output impedance to drive loads. The DAC8881 operates from a single analog power supply that
ranges from 2.7V to 5.5V, and typically consumes 850 μ A when operating with a 3V supply. Data are written to
the device in a 16-bit word format, via an SPI serial interface. To enable compatibility with 1.8V, 3V, or 5V logic
families, an IOV
DD
supply pin is provided. This pin allows the DAC8881 input and output logic to be powered
from the same logic supply used to interface signals to and from the device. Internal voltage translators are
included in the DAC8881 to interface digital signals to the device core. Separate AV
DD
and DV
DD
supply pins are
provided, but should be connected together. See Figure 67 for the basic configuration of the DAC8881.
To ensure a known power-up state, the DAC8881 is designed with a power-on reset function. Upon power-up,
the DAC8881 is reset to either zero-scale or midscale depending on the state of the RSTSEL pin. The device
can also be hardware reset by using the RST and RSTSEL pins.
Figure 66. DAC8881 Architecture
22 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): DAC8881