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0 1 2 3 4 5
I (mA)
SINK
0.25
0.20
0.15
0.10
0.05
0
V (V)
OUT
DACLoadedwith0200h
DACLoadedwith0800h
DACLoadedwith0400h
DACLoadedwith0000h
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.54.0 5.0
LogicInputVoltage(V)
200
180
160
140
120
100
80
60
40
20
0
IOV SupplyCurrent( A)m
DD
IOV =5V
DD
IOV =2.7V
DD
Time(2ms/div)
2V/div 1mV/div
5V/div
Large-SignalOutput
LDAC
Signal
CodeChange:0000htoFFFFh
OutputLoadedwith10k andW
50pFtoAGND
Small-SignalError
Time(2 s/div)m
2V/div
1mV/div
5V/div
Large-SignalOutput
LDAC
Signal
CodeChange:FFFFhto0000h
OutputLoadedwith10k andW
50pFtoAGND
Small-SignalError
Time(2 s/div)m
2V/div
1mV/div
5V/div
Large-SignalOutput
LDAC
Signal
CodeChange:1000htoF000h
OutputLoadedwith10k andW
50pFtoAGND
Small-SignalError
Time(2 s/div)m
2V/div
1mV/div
5V/div
Large-SignalOutput
LDAC
Signal
CodeChange:F000hto1000h
OutputLoadedwith10k andW
50pFtoAGND
Small-SignalError
DAC8881
SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007
TYPICAL CHARACTERISTICS: V
DD
= +5V (continued)
At T
A
= +25 ° C, V
REFH
= +5.0V, V
REFL
= 0V, and Gain = 1X Mode, unless otherwise noted.
OUTPUT VOLTAGE
vs DRIVE CURRENT CAPABILITY IOV
DD
SUPPLY CURRENT
(Operation Near AGND Rail) vs LOGIC INPUT VOLTAGE
Figure 28. Figure 29.
LARGE SIGNAL LARGE SIGNAL
SETTLING TIME SETTLING TIME
Figure 30. Figure 31.
LARGE SIGNAL LARGE SIGNAL
SETTLING TIME SETTLING TIME
Figure 32. Figure 33.
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