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DAC8881

FEATURES DESCRIPTION

APPLICATIONS

(1)

Control

Logic

DGND IOV

AGND AV

V -S

REFH

V -F

REFH

RST

RSTSEL

USB/BTC

GAIN

SDI

SCLK

SPIInterface

ShiftRegister

Input

DAC

Latch

LDAC V -S

REFL

V -F

REFL

Resistor

Network

DAC

NOTE:(1) R =5k forgain=1,W

R =10k forgain=2.W

DAC8881

SerialOut

Control

SDOSEL

SDO

Power-On

Reset

PDN

OUT

DAC8881

SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007

16-Bit, Single-Channel, Low-Noise, Voltage-Output

DIGITAL-TO-ANALOG CONVERTER

2345

• Relative Accuracy: ± 0.5 LSB

The DAC8881 is a 16-bit, single-channel,

voltage-output digital-to-analog converter (DAC) that

• 16-Bit Monotonic Over Temperature Range

offers low-power operation and a flexible SPI serial

• Low-Noise: 24nV/ √ Hz

interface. It also features 16-bit monotonicity,

• Fast Settling: 5 μ s

excellent linearity, and fast settling time. The on-chip

• On-Chip Output Buffer Amplifier with precision output amplifier allows rail-to-rail output

swing to be achieved over the full supply range of

Rail-to-Rail Operation

2.7V to 5.5V.

• Wide, Single Power Supply: +2.7V to +5.5V

The device supports a standard SPI serial interface

• DAC Loading Control

capable of operating with input data clock frequencies

• Selectable Power-On Reset to Zero-Scale or

up to 50MHz. The DAC8881 requires an external

Midscale

reference voltage to set the output range of the DAC

• Power-Down Mode

channel. A programmable power-on reset circuit is

also incorporated into the device to ensure that the

• Unipolar Straight Binary or

DAC output powers up at zero-scale or midscale, and

2's Complement Input Mode

remains there until a valid write command.

• Fast SPI™ Interface with Schmitt-Triggered

Additionally, the device has the capability to function

Inputs:

in either unipolar straight binary or 2's complement

Up To 50MHz, 1.8V/3V/5V Logic

mode. The DAC8881 provides a power-down feature,

• Small Package: QFN-24, 4x4mm

accessed over the PDN pin, that reduces the current

consumption to 25 μ A at 5V. Power consumption is

6mW at 5V, reducing to 125 μ W in power-down mode.

• Industrial Process Control

The DAC8881 is available in a 4x4mm QFN-24

• Data Acquisition Systems

package with a specified operating temperature range

• Automatic Test Equipment

of – 40°C to +105°C.

• Communications

• Optical Networking

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 DSP is a trademark of Texas Instruments.

3 SPI, QSPI are trademarks of Motorola, Inc.

4 MICROWIRE is a trademark of National Semiconductor.

5 All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (37 pages)

PAGE 1
DA DAC8881 C8 88 1 SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007 16-Bit, Single-Channel, Low-Noise, Voltage-Output DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION 1 • • • • • 2345 • • • • • • • Relative Accuracy: ±0.5 LSB 16-Bit Monotonic Over Temperature Range Low-Noise: 24nV/√Hz Fast Settling: 5μs On-Chip Output Buffer Amplifier with Rail-to-Rail Operation Wide, Single Power Supply: +2.7V to +5.
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DAC8881 www.ti.com SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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DAC8881 www.ti.com SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007 ELECTRICAL CHARACTERISTICS All specifications at TA = TMIN to TMAX, AVDD = DVDD = +2.7V to +5.5V, IOVDD = +1.8V to +5.5V, gain = 1X mode, unless otherwise noted. DAC8881 PARAMETER CONDITIONS MIN TYP MAX UNIT ±0.5 ±1 LSB ±0.
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DAC8881 www.ti.com SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007 ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = TMIN to TMAX, AVDD = DVDD = +2.7V to +5.5V, IOVDD = +1.8V to +5.5V, gain = 1X mode, unless otherwise noted. DAC8881 PARAMETER CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS (3) High-level input voltage, VIH Low-level input voltage, VIL IOVDD = 4.5V to 5.5V 3.8 IOVDD + 0.3 V IOVDD = 2.7V to 3.3V 2.1 IOVDD + 0.3 V IOVDD = 1.7V to 2.0V 1.5 IOVDD + 0.
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DAC8881 www.ti.com SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007 PIN CONFIGURATION (1) SDO DGND DVDD SDOSEL CS 22 21 20 19 IOVDD 24 23 RGE PACKAGE(1) QFN-24 (TOP VIEW) SCLK 1 18 PDN SDI 2 17 RST LDAC 3 16 USB/BTC AGND 4 15 GAIN AVDD 5 14 RSTSEL VREFL-S 6 13 NC DAC8881 10 11 12 NC RFB VREFL-F 9 VOUT VREFH-F 7 8 VREFH-S (Thermal Pad) The thermal pad is internally connected to the substrate. This pad can be connected to the analog ground or left floating.
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DAC8881 www.ti.com SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007 TIMING DIAGRAMS Case 1: Standalone operation without SDO, LDAC tied low. t1 t2 CS t3 t4 t7 t6 t5 Input Register and DAC Latch Updated SCLK t8 Bit 15 (N) SDI LDAC t9 Bit 14 (N) Bit 1 (N) Bit 0 (N) Low Case 2: Standalone operation without SDO, LDAC active.
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DAC8881 www.ti.com SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007 TIMING CHARACTERISTICS for Figure 1 (1) (2) (3) At –40°C to +105°C, unless otherwise noted.
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DAC8881 www.ti.com SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007 Case 1: Standalone operation with output from SDO, LDAC tied low. t1 t2 CS Input Register and DAC Latch Updated t3 t4 t7 t6 t5 SCLK t8 Bit 15 (N) SDI t9 Bit 14 (N) Bit 1 (N) t11 High-Z SDO LDAC Bit 15 (N - 1) from Input Reg. Bit 14 (N - 1) from Input Reg. Bit 0 (N) t12 t13 Bit 1 (N - 1) from Input Reg. Bit 0 (N - 1) from Input Reg. High-Z t10 Low Case 2: Standalone operation with output from SDO, LDAC active.
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DAC8881 www.ti.com SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007 Case 1: Daisy Chain, LDAC tied low. t1 t2 CS Input Register and DAC Latch Updated t3 t4 t7 t6 t5 SCLK t8 Bit 15 (N) SDI t9 Bit 14 (N) Bit 0 (N) Bit 15 (N + 1) t11 LDAC t12 t13 Bit 15 (N) High-Z SDO Bit 0 (N + 1) Bit 0 (N) High-Z t10 Low Case 2: Daisy Chain, LDAC active.
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DAC8881 www.ti.com SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007 TIMING CHARACTERISTICS for Figure 2 and Figure 3 (1) (2) (3) At –40°C to +105°C, unless otherwise noted.
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DAC8881 www.ti.com SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS: VDD = +5V At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted. LINEARITY ERROR vs DIGITAL INPUT CODE 1.0 1.0 TA = +25°C 0.8 0.6 0.6 0.4 0.4 0.2 0 -0.2 -0.4 0 -0.2 -0.4 -0.6 -0.8 -0.8 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code Figure 4. Figure 5.
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DAC8881 www.ti.com SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS: VDD = +5V (continued) At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted. LINEARITY ERROR vs TEMPERATURE DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE 1.0 1.0 0.8 0.8 0.6 INL Max 0.4 DNL Error (LSB) INL Error (LSB) 0.6 0.2 0 -0.2 INL Min -0.4 0 -0.2 DNL Min -0.4 -0.6 -0.8 -0.8 -1.
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DAC8881 www.ti.com SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS: VDD = +5V (continued) At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted. DIFFERENTIAL LINEARITY ERROR vs REFERENCE VOLTAGE 1.0 1.0 0.8 0.8 0.6 0.6 0.4 DNL Error (LSB) INL Error (LSB) LINEARITY ERROR vs REFERENCE VOLTAGE INL Max 0.2 0 -0.2 INL Min -0.4 0 -0.2 DNL Min -0.4 -0.6 -0.8 -0.8 -1.
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DAC8881 www.ti.com SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS: VDD = +5V (continued) At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted. AVDD SUPPLY CURRENT vs TEMPERATURE AVDD POWER-DOWN CURRENT vs TEMPERATURE 50 1000 AVDD Supply Current (mA) AVDD Supply Current (mA) 1200 800 VREFH = 5.0V VREFL = 0V Gain = 1X Mode 600 VREFH = 2.5V VREFL = 0V Gain = 2X Mode 400 200 40 30 AVDD = 5.0V 20 AVDD = 2.
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DAC8881 www.ti.com SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS: VDD = +5V (continued) At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted. OUTPUT VOLTAGE vs DRIVE CURRENT CAPABILITY (Operation Near AGND Rail) IOVDD SUPPLY CURRENT vs LOGIC INPUT VOLTAGE 200 0.25 IOVDD Supply Current (mA) 180 0.20 VOUT (V) DAC Loaded with 0800h 0.15 DAC Loaded with 0400h 0.10 DAC Loaded with 0200h 0.05 IOVDD = 5V 160 140 120 100 80 60 40 IOVDD = 2.
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DAC8881 www.ti.com SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS: VDD = +5V (continued) At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted. LARGE SIGNAL SETTLING TIME (GAIN = 2X MODE) VREFH = 2.5V LARGE SIGNAL SETTLING TIME (GAIN = 2X MODE) Code Change: FFFFh to 0000h Output Loaded with 10kW and 50pF to AGND VREFH = 2.
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DAC8881 www.ti.com SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS: VDD = +5V (continued) At TA = +25°C, VREFH = +5.0V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted. MAJOR CARRY GLITCH MAJOR CARRY GLITCH Code Change: 7FFFh to 8000h Output Loaded with 10kW and 50pF to AGND Gain = 1X Mode VREFH = +2.5V Gain = 1X Mode VREFH = +2.
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DAC8881 www.ti.com SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS: VDD = +2.7V At TA = +25°C, VREFH = +2.5V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted. LINEARITY ERROR vs DIGITAL INPUT CODE 1.0 1.0 TA = +25°C 0.8 0.6 0.6 0.4 0.4 0.2 0 -0.2 -0.4 0 -0.2 -0.4 -0.6 -0.8 -0.8 -1.0 0 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code 0 Figure 45. LINEARITY ERROR vs DIGITAL INPUT CODE DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1.
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DAC8881 www.ti.com SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS: VDD = +2.7V (continued) At TA = +25°C, VREFH = +2.5V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted. LINEARITY ERROR vs REFERENCE VOLTAGE 1.0 1.0 0.8 0.8 0.6 0.6 INL Max 0.2 0 -0.2 0.4 DNL Error (LSB) 0.4 INL Error (LSB) DIFFERENTIAL LINEARITY ERROR vs REFERENCE VOLTAGE INL Min -0.4 0 -0.2 -0.6 -0.6 -0.8 -0.8 -1.0 0 0.5 1.0 1.5 2.0 VREFH Reference Voltage (V) 2.5 3.0 0 0.5 1.0 1.
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DAC8881 www.ti.com SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS: VDD = +2.7V (continued) At TA = +25°C, VREFH = +2.5V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted. OUTPUT VOLTAGE vs DRIVE CURRENT CAPABILITY (Operation Near AVDD Rail) OUTPUT VOLTAGE vs DRIVE CURRENT CAPABILITY (Operation Near AGND Rail) 2.70 0.25 DAC Loaded with FFFFh 2.65 VOUT (V) 2.60 DAC Loaded with FE00h 2.55 DAC Loaded with FC00h 2.50 VOUT (V) 0.
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DAC8881 www.ti.com SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007 TYPICAL CHARACTERISTICS: VDD = +2.7V (continued) At TA = +25°C, VREFH = +2.5V, VREFL = 0V, and Gain = 1X Mode, unless otherwise noted. MAJOR CARRY GLITCH MAJOR CARRY GLITCH Code Change: 7FFFh to 8000h Output Loaded with 10kW and 50pF to AGND Gain = 1X Mode VREFH = +2.5V Gain = 1X Mode VREFH = +2.5V Integrated Glitch Energy (17.5nV-s) 100mV/div VOUT Signal VOUT Signal 100mV/div Integrated Glitch Energy (16.
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DAC8881 www.ti.com SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007 THEORY OF OPERATION GENERAL DESCRIPTION The DAC8881 is a single-channel, 16-bit, serial-input, voltage-output digital-to-analog converter (DAC). The architecture is an R-2R ladder configuration with the four MSBs segmented, followed by an operational amplifier that serves as a buffer, as shown in Figure 66. The on-chip output buffer allows rail-to-rail output swings while providing a low output impedance to drive loads.
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DAC8881 www.ti.com SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007 SDOSEL Chip-Select CS 19 SDOSEL 20 DVDD 21 22 SDO 4 15 14 5 (Thermal Pad) VOUT VREFH-S 13 RST Reset DAC Registers USB/BTC GAIN RSTSEL NC 12 6 7 VREFL-S DAC8881 PDN NC AVDD 16 3 11 AGND 17 VREFH-F Load DAC Registers 2 10 LDAC 18 9 Serial Data In 1 VREFL-F SDI 8 SCLK Clock 23 1mF IOVDD + 24 0.1mF DGND 1mF RFB + 1.8V to 5V 0.1mF Serial Data Out +5V 0V to +5.0V External Reference +5.
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DAC8881 www.ti.com SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007 ANALOG OUTPUT The DAC8881 offers a force and sense output configuration for the high open-loop gain output amplifier. This feature allows the loop around the output amplifier to be closed at the load (as shown in Figure 68), thus ensuring an accurate output voltage. The output buffer VOUT and RFB pins are provided so that the output op amp buffer feedback can be connected at the load.
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DAC8881 www.ti.com SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007 REFERENCE INPUTS The reference high input, VREFH, can be set to any voltage in the range of 1.25V to AVDD. The reference low input, VREFL, can be set to any voltage in the range of –0.2V to +0.2V (to provide a small offset to the output of the DAC8881, if desired). The current into VREFH and out of VREFL depends on the DAC code, and can vary from approximately 0.5mA to 1mA in the gain = 1X mode of operation.
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DAC8881 www.ti.com SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007 OUTPUT RANGE The maximum output range of the DAC8881 is VREFL to VREFH × G, where G is the output buffer gain set by the GAIN pin. When the GAIN pin is connected to DGND, the output buffer gain = 1. When the GAIN pin is connected to IOVDD, the output buffer gain = 2. The output range must not be greater than AVDD; otherwise, output saturation occurs.
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DAC8881 www.ti.com SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007 POWER-ON RESET The DAC8881 has a power-on reset function. After power-on, the value of the input register, the DAC latch, and the output from the VOUT pin are set to the value defined by the RSTSEL pin.
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DAC8881 www.ti.com SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007 on the next DAC in the chain, a multi-DAC interface is constructed. 16 clock pulses are required for each DAC in the system. Therefore, the total number of clock cycles must be equal to (16 x N), where N is the total number of devices in the chain. When the serial transfer to all devices is complete, CS should be taken high. This action prevents any further data from being clocked into the input shift register.
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DAC8881 www.ti.com SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007 APPLICATION INFORMATION BIPOLAR OPERATION USING THE DAC8881 The DAC8881 is designed for single-supply operation; however, a bipolar output range is also possible using the circuit shown in Figure 72. This circuit gives a bipolar output voltage range of VBIP, where VBIP is represented by Equation 2. Note that for this circuit to work, the DAC8881 must operate in the gain = 1X mode configuration with GAIN = DGND.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC8881SRGER VQFN RGE 24 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 DAC8881SRGET VQFN RGE 24 250 180.0 12.4 4.3 4.3 1.5 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC8881SRGER VQFN RGE 24 3000 338.1 338.1 20.6 DAC8881SRGET VQFN RGE 24 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.