Datasheet

TIMING CHARACTERISTICS: V
DD
= +5V
(1) (2)
DAC8871
www.ti.com ............................................................................................................................................................. SBAS396A – JUNE 2007 – REVISED JUNE 2008
At – 40 ° C to +105 ° C, unless otherwise noted.
PARAMETER MIN MAX UNIT
t
SCK
SCLK period 20 ns
t
WSCK
SCLK high or low time 10 ns
t
Delay
Delay from SCLK high to CS low 10 ns
t
Lead
CS enable lead time 10 ns
t
Lag
CS enable lag time 10 ns
t
DSCLK
Delay from CS high to SCLK high 10 ns
t
TD
CS high between active period 30 ns
t
SU
Data setup time (input) 10 ns
t
HO
Data hold time (input) 0 ns
t
WLDAC
LDAC width 30 ns
t
DLDAC
Delay from CS high to LDAC low 30 ns
t
RST
Reset ( RST) low 10 ns
V
DD
high to CS low (power-up delay) 10 µ s
(1) Assured by design. Not production tested.
(2) Sample tested during the initial release and after any redesign or process changes that may affect this parameter.
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