Datasheet

TIMING DIAGRAMS
SCLK
SDI
CS
t
Delay
t
Lead
t
SCK
Bit15(MSB) Bit14
LOW
Bit0
DAC
Updated
Bit13,...,Bit1
t
WSCK
t
WSCK
t
RST
t
TD
t
DSCLK
t
Lag
t
HO
t
SU
LDAC
RST
Don’t Care--
t
Delay
t
Lead
HIGH
DAC
Updated
Bit15(MSB) Bit14 Bit0Bit13,...,Bit1
t
SCK
t
WSCK
t
WSCK
t
RST
t
TD
t
DSCLK
t
WLDAC
t
DLADC
t
Lag
t
HO
t
SU
SCLK
SDI
CS
LDAC
RST
Don’t Care--
DAC8871
SBAS396A – JUNE 2007 – REVISED JUNE 2008 ............................................................................................................................................................. www.ti.com
Figure 1. Case 1 — LDAC Tied Low
Figure 2. Case 2 — LDAC Active
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