Datasheet

PIN CONFIGURATION (NOT TO SCALE)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DGND
LDAC
SDI
SCLK
CS
RST
RSTSEL
V
DD
V
OUT
V
CC
V
SS
AGND
V -F
REFH
V -S
REFH
V -S
REFL
V -F
REFL
DAC8871
DAC8871
www.ti.com ............................................................................................................................................................. SBAS396A – JUNE 2007 – REVISED JUNE 2008
PW PACKAGE
TSSOP-16
(TOP VIEW)
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NO. NAME
1 V
OUT
Analog output of the DAC
2 V
CC
Positive analog power supply: +15V
3 V
SS
Negative analog power supply: – 15V
4 AGND Analog ground
5 V
REFH-
F V
REFH
reference input (Force). Connect to external V
REFH
.
6 V
REFH-
S V
REFH
reference input (Sense). Connect to external V
REFH
.
7 V
REFL-
S V
REFL
reference input (Sense). Connect to external V
REFL
.
8 V
REFL-
F V
REFL
reference input (Force). Connect to external V
REFL
.
9 V
DD
Digital power. +5V for 5V interface logic; +3V for 3V logic.
Power-On-Reset select. Determines V
OUT
after power-on reset. If tied to V
DD
, the DAC latch is set to mid-scale
10 RSTSEL
after power-on, and V
OUT
is (V
REFH
– V
REFL
)/2. If tied to DGND, the DAC latch is cleared ( ' 0 ' ), and V
OUT
is V
REFL
.
11 RST Reset (active low)
12 CS Chip select input (active low). Data are not clocked into SDI unless CS is low.
13 SCLK Serial clock input
14 SDI Serial data input. Data are latched into input register on the rising edge of SCLK.
Load DAC control input (active low). When LDAC is low, the DAC latch is simultaneously updated with the content
15 LDAC
of the input register.
16 DGND Digital ground
Copyright © 2007 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): DAC8871