Datasheet
APPLICATION INFORMATION
REFERENCE INPUT
OPA2277
V -F
REFH
V -S
REFH
V
REFH
DAC8871
OPA2277
V -F
REFL
V -S
REFL
V
REFL
POWER-SUPPLY BYPASSING
POWER-SUPPLY SEQUENCING
DAC8871
SBAS396A – JUNE 2007 – REVISED JUNE 2008 .............................................................................................................................................................
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The DAC full-scale output voltage is determined by the reference voltage, as shown in the Output Range section.
Reference input V
REFH
can be any voltage from 0V to +18V. Reference input V
REFL
can be any voltage from
– 18V to (V
REFH
– 1.25V). The current into the V
REFH
input and out of V
REFL
depends on the DAC output voltages.
Refer to Figure 27 and Figure 28 for details. The reference input appears as a varying load to the reference. If
the reference can sink or source the required current, a reference buffer is not required. The DAC8871 features a
reference drive (force) and sense connection that minimizes the internal errors caused by the changing reference
current and the circuit impedances. Figure 40 shows a typical reference configuration.
Figure 40. Buffered Reference Connection
For accurate, high-resolution performance, bypassing the supply pins with a 10 µ F tantalum capacitor in parallel
with a 0.1 µ F ceramic capacitor is recommended.
The analog supplies (V
CC
and V
SS
) must power up before the digital supply (V
DD
). All three supplies must power
up before the reference voltages (V
REFH
and V
REFL
) are applied. Additionally, because the DAC input shift
register is not reset during a power-on reset (or a hardware reset through the RST pin), the CS pin must not be
unintentionally asserted during power-up of the device. It is recommended that the CS pin be connected to V
DD
through a pull-up resistor to avoid improper power-up.
Likewise, the state of the LDAC pin must not be accidentally changed during power-up. It is recommended that
the LDAC pin be connected to V
DD
through a pull-up resistor, unless it is permanently tied to ground.
To ensure that the ESD protection circuitry of this device is not activated, all other digital pins must be kept at
ground potential until V
DD
is applied.
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