Datasheet

EVM Operation

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3.4 Digital Interface Control

The DAC8831EVM is designed for easy interfacing to multiple control platforms. Table 4 provides the

pinout of connector J2. Samtec part numbers SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a

convenient 10-pin dual row header/socket combination at J2. This header/socket provides access to the

digital control and serial data pins of the DAC8831EVM. Consult Samtec at www.samtec.com, or call

1-800-SAMTEC-9 for a variety of mating connector options.

Table 4. Pinout of J2

Pin Number Signal Description

J2-1 Unused

J2-3 SCLK Serial Clock

J2-5 Unused

J2-7 CS Select to the DAC. Tied to the Frame Sync for DSP host systems – STE for SPI™ Host

systems

J2-9 Unused

J2-11 SDI Serial Data Input

J2-13 Unused

J2-15 Unused

J2-17 LDAC Load DAC – Active low signal; enables DAC output updates – jumper configurable (see

schematic). When LDAC is Low, the DAC latch is simultaneously updated with the

content of the input register. Can be controlled by GPIO or tied low via W3.

J2-19 Unused

3.5 Analog Output

The analog output is applied directly to J1 (top or bottom side) and can be further applied to optional

amplifier and signal conditioning modules. The analog output range depends on the configuration of the

EVM and the external reference applied at J1-20 or TP2. See Section 3.1 of this user guide and the

DAC8831 data sheet (SLAS449) or the DAC8832 data sheet (SBAS380) to determine the maximum

analog output range.

3.6 Load DAC (LDAC)

Jumper W2 is provided to allow the selection of the signals applied to the DAC8831 or DAC8832 LDAC

pin. The factory default condition for the EVM is to place a shunt jumper between pins 1-2 of W3. This ties

the LDAC pin directly to ground for simultaneous updates of the DAC output buffer. When the shunt is

moved to pins 2-3, an external LDAC signal may be applied to J2-17 to allow timed updates of the DAC

output buffer.

DAC8831/32 Evaluation Module SLAU202A–December 2006–Revised November 2009

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