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BIT14
BIT13,...,1
BIT15(MSB) BIT0
DAC
Updated
t
Delay
t
Lead
t
wsck
t
td
t
wsck
t
Lag
t
DSCLK
t
su
t
ho
CS
SCLK
SDI
t
sck
---Don'tCare
DAC
Updated
−−−Don’tCare
t
Delay
t
Lead
t
wsck
t
td
t
wsck
t
Lag
t
DSCLK
t
su
t
ho
CS
SCLK
SDI
LOW
LDAC
DAC
Updated
−−−Don’tCare
t
Delay
t
Lead
t
wsck
t
td
t
wsck
t
Lag
t
DSCLK
t
su
t
ho
CS
SCLK
SDI
HIGH
LDAC
Case1: LDAC tiedtoLOW
Case2: LDAC Active
t
DLADC
t
WLDAC
t
sck
t
sck
BIT 15(MSB) BIT 14 BIT 13,...,1 BIT 0
BIT 15(MSB) BIT 14 BIT 13,...,1 BIT 0
DAC8830
DAC8831
SLAS449D – FEBRUARY 2005 – REVISED SEPTEMBER 2007
Figure 1. DAC8830 Timing Diagram
Figure 2. DAC8831 Timing Diagram
6 Submit Documentation Feedback Copyright © 2005 – 2007, Texas Instruments Incorporated
Product Folder Link(s): DAC8830 DAC8831