Datasheet
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APPLICATION INFORMATION
Multiplying Mode THD vs Frequency
Stability Circuit
DAC8820
OPA277
V
DD
V
DD
U2
GND
R
OFS
R
FB
V
OUT
I
OUT
V
REF
V
REF
U1
C1
Bipolar Output Circuit
DAC8820
SBAS358D – AUGUST 2005 – REVISED FEBRUARY 2008
Figure 35 and Figure 36 show the DAC8820 bipolar 4-quadrant multiplying mode total harmonic distortion (THD)
versus frequency. Figure 35 shows the bipolar multiplying mode THD with the DAC8820 set to a full-scale code
of FFFFh. Figure 36 shows the bipolar multiplying mode THD with the DAC8820 set to a minus full scale code of
0000h. In both graphs, two OPA627 s are used for both the DAC output op amp and the reference inverting
amplifier. A 6 V
RMS
sine wave is used for the reference input V
REF
and is swept in frequency from 10 Hz to 30
kHz. The THD levels versus frequency are illustrated at various DAC output filtering levels using an external
ac-coupled low-pass filter.
Figure 37 illustrates the DAC8820 unipolar 2-quadrant multiplying mode THD versus frequency. The DAC8820 is
set to a full-scale code of FFFFh. A single OPA627 is used for the DAC output op amp.
For a current-to-voltage (I/V) design, as shown in Figure 41 , the DAC8820 current output (I
OUT
) and the
connection with the inverting node of the op amp should be as short as possible and laid out according to correct
printed circuit board (PCB) layout design. For each code change there is a step function. If the gain bandwidth
product (GBP) of the op amp is limited and parasitic capacitance is excessive at the inverting node, then gain
peaking is possible. Therefore, a compensation capacitor C1 (4 pF to 20 pF, typ) can be added to the design for
circuit stability, as shown in Figure 41 .
Figure 41. Gain Peaking Prevention Circuit with Compensation Capacitor
The DAC8820, as a 4-quadrant multiplying DAC, can be used to generate a bipolar output. The polarity of the
full-scale output (I
OUT
) is the inverse of the input reference voltage at V
REF
.
Using a dual op amp, such as the OPA2277 , full 4-quadrant operation can be achieved with minimal
components. Figure 42 demonstrates a ± 10 V
OUT
circuit with a fixed +10 V reference.
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