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ShiftRegister
Address
Decoder
ToInputRegister
A
B
C
D
19th
Clock
CS
CLK
SDI
SDO
POWER ON RESET
ESD Protection Circuits
250 W
V
DD
DGND
Digital
Inputs
DAC8814
SBAS338D – JANUARY 2005 – REVISED SEPTEMBER 2006
Figure 61. DAC8814 Equivalent Logic Interface
Two additional pins RS and MSB provide hardware control over the preset function and DAC register loading. If
these functions are not needed, the RS pin can be tied to logic high. The asynchronous input RS pin forces all
input and DAC registers to either the zero-code state (MSB = 0), or the half-scale state (MSB = 1).
When the V
DD
power supply is turned on, an internal reset strobe forces all the Input and DAC registers to the
zero-code state or half-scale, depending on the MSB pin voltage. The V
DD
power supply should have a smooth
positive ramp without drooping in order to have consistent results, especially in the region of V
DD
= 1.5 V to
2.3 V. The DAC register data stays at zero or half-scale setting until a valid serial register data load takes place.
All logic-input pins contain back-biased ESD protection zener diodes connected to ground (DGND) and V
DD
as
shown in Figure 62 .
Figure 62. Equivalent ESD Protection Circuits
19
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