Datasheet
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D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A0
A1
A
B
C
D
DAC
2:4
Decode
Input
Register
R
Input
Register
R
Input
Register
R
Input
Register
R
DAC A
Register
R
DAC B
Register
R
DAC C
Register
R
DAC D
Register
R
DAC A
DAC B
DAC C
DAC D
Set MSB
Set
MSB
Power-
On
Reset
DGND MSB LDAC RS
A
GND
F
A
GND
D
I
OUT
D
R
FB
D
A
GND
C
I
OUT
C
R
FB
C
A
GND
B
I
OUT
C
R
FB
B
A
GND
A
I
OUT
A
R
FB
A
V
DD
A B C DV
REF
CS
CLK
SDI
SDO
EN
SERIAL DATA INTERFACE
DAC8814
SBAS338D – JANUARY 2005 – REVISED SEPTEMBER 2006
Figure 60. System Level Digital Interfacing
The DAC8814 uses a 3-wire ( CS, SDI, CLK) SPI-compatible serial data interface. Serial data of the DAC8814 is
clocked into the serial input register in an 18-bit data-word format. MSB bits are loaded first. Table 2 defines the
18 data-word bits for the DAC8814.
Data is placed on the SDI pin, and clocked into the register on the positive clock edge of CLK subject to the data
setup and data hold time requirements specified in the Interface Timing Specifications. Data can only be clocked
in while the CS chip select pin is active low. For the DAC8814, only the last 18 bits clocked into the serial
register are interrogated when the CS pin returns to the logic high state.
Since most microcontrollers output serial data in 8-bit bytes, three right-justified data bytes can be written to the
DAC8814. Keeping the CS line low between the first, second, and third byte transfers results in a successful
serial register update.
Once the data is properly aligned in the shift register, the positive edge of the CS initiates the transfer of new
data to the target DAC register, determined by the decoding of address bits A1and A0. For the DAC8814,
Table 1 , Table 2 , Table 3 and Figure 57 define the characteristics of the software serial interface. Figure 61
shows the equivalent logic interface for the key digital control pins for the DAC8814.
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