Datasheet

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OPA277
DAC8806
V
DD
V
DD
+15V
U2
GND
R
OFS
R
FB
V
OUT
I
OUT
V
REF
V+
-15V
V-
U1
t
WR
t
DS
t
DH
t
LWD
t
LDAC
t
RST
WR
DATA
LDAC
RST
DAC8806
SBAS385B – APRIL 2006 – REVISED FEBRUARY 2008
Figure 39. Voltage Output Configuration
Figure 40. DAC8806 Timing Diagram
Table 1. Function of Control Inputs
CONTROL INPUTS
RST WR LDAC REGISTER OPERATION
Asynchronous operation. The DAC register is set to zero code, resulting in the DAC output being set
0 X X
to 0 V. The DAC input register contents are not reset by the RST signal.
1 0 0 Load the input register with all 14 data bits.
1 1 1 Load the DAC register with the contents of the input register.
1 0 1 The input and DAC register are transparent.
LDAC and WR are tied together and programmed as a pulse. The 14 data bits are loaded into the
1 input register on the falling edge of the pulse and then loaded into the DAC register on the rising
edge of the pulse.
1 1 0 No register operation.
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