Datasheet

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DAC8805

SBAS391A – DECEMBER 2006 – REVISED MAY 2007

Table 2. Address Decoder Pins

A1 A0 OUTPUT UPDATE

0 0 DAC A

0 1 None

1 0 DAC A and DAC B

1 1 DAC B

Table 3. Function of Control Inputs

CONTROL INPUTS

RS WR LDAC REGISTER OPERATION

Asynchronous operation. Reset the input and DAC register to '0' when the RSTSEL pin is tied to DGND, and to

0 X X

midscale when RSTSEL is tied to V

1 0 0 Load the input register with all 14 data bits.

1 1 1 Load the DAC register with the contents of the input register.

1 0 1 The input and DAC register are transparent.

LDAC and WR are tied together and programmed as a pulse. The 14 data bits are loaded into the input register on

the falling edge of the pulse and then loaded into the DAC register on the rising edge of the pulse.

1 1 0 No register operation.

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