Datasheet

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APPLICATION INFORMATION
DIGITAL INTERFACE
STABILITY CIRCUIT
C
1
DAC8805
V
REF
U2
I A/B
OUT
V
DD
R
OFS
R
FB
U1
V
DD
GND
V
REF
OPA277
V
OUT
DAC8805
SBAS391A – DECEMBER 2006 – REVISED MAY 2007
The parallel bus interface of the DAC8805 is comprised of a 14-bit data bus, D0—D13, address lines A0 and A1,
and a WR control signal. Timing and control functionality are shown in Figure 1 , and described in Table 2 and
Table 3 . The address lines must be set up and stable before the WR signal goes low, to prevent loading
improper data to an undesired input register.
Both channels of the DAC8805 can be simultaneously updated by control of the LDAC signal, as shown in
Figure 1 . Reset control ( RS) and reset select control (RSTSEL) signals are provided to allow user reset ability to
either zero scale or midscale codes of both the input and DAC registers.
For a current-to-voltage (I/V) design, as shown in Figure 42 , the DAC8805 current output (I
OUT
) and the
connection with the inverting node of the op amp should be as short as possible and laid out according to
correct printed circuit board (PCB) layout design. For each code change, there is an output step function. If the
gain bandwidth product (GBP) of the op amp is limited and parasitic capacitance is excessive at the inverting
node, then gain peaking is possible. Therefore, a compensation capacitor C
1
(4pF to 20pF, typ) can be added to
the design for circuit stability, as shown in Figure 42 .
Figure 42. Gain Peaking Prevention Circuit with Compensation Capacitor
16
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