Datasheet

www.ti.com

Shift Register

Address

Decoder

To Input Register

17th

Clock

CLK

SDI

SDO

POWER ON RESET

ESD Protection Circuits

250 W

DGND

Digital

Inputs

DAC8803

SBAS340C – JANUARY 2005 – REVISED FEBRUARY 2006

Once the data is properly aligned in the shift register, the positive edge of the CS initiates the transfer of new

data to the target DAC register, determined by the decoding of address bits A1and A0. For the DAC8803,

Table 2 and Table 3 define the characteristics of the software serial interface. Figure 61 shows the equivalent

logic interface for the key digital control pins for the DAC8803.

Figure 61. DAC8803 Equivalent Logic Interface

Two additional pins RS and MSB provide hardware control over the preset function and DAC register loading. If

these functions are not needed, the RS pin can be tied to logic high. The asynchronous input RS pin forces all

input and DAC registers to either the zero-code state (MSB = 0), or the half-scale state (MSB = 1).

When the V

power supply is turned on, an internal reset strobe forces all the Input and DAC registers to the

zero-code state or half-scale, depending on the MSB pin voltage. The V

power supply should have a smooth

positive ramp without drooping in order to have consistent results, especially in the region of V

= 1.5 V to

2.3 V. The DAC register data stays at zero or half-scale setting until a valid serial register data load takes place.

All logic-input pins contain back-biased ESD protection zener diodes connected to ground (DGND) and V

shown in Figure 62 .

Figure 62. Equivalent ESD Protection Circuits

Submit Documentation Feedback