Datasheet
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D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
A0
A1
A
B
C
D
DAC
2:4
Decode
Input
Register
R
Input
Register
R
Input
Register
R
Input
Register
R
DAC A
Register
R
DAC B
Register
R
DAC C
Register
R
DAC D
Register
R
DAC A
DAC B
DAC C
DAC D
Set MSB
Set
MSB
Power-
On
Reset
DGND MSB LDAC
RS
A
GND
F
A
GND
D
I
OUT
D
R
FB
D
A
GND
C
I
OUT
C
R
FB
C
A
GND
B
I
OUT
C
R
FB
B
A
GND
A
I
OUT
A
R
FB
A
V
DD
A B C DV
REF
CS
CLK
SDI
SDO
EN
14
SERIAL DATA INTERFACE
DAC8803
SBAS340C – JANUARY 2005 – REVISED FEBRUARY 2006
Figure 60. System Level Digital Interfacing
The DAC8803 uses a 3-wire ( CS, SDI, CLK) SPI-compatible serial data interface. Serial data of the DAC8803 is
clocked into the serial input register in a 16-bit data-word format. MSB bits are loaded first. Table 2 defines the
16 data-word bits for the DAC8803.
Data is placed on the SDI pin, and clocked into the register on the positive clock edge of CLK subject to the data
setup and data hold time requirements specified in the Interface Timing Specifications. Data can only be clocked
in while the CS chip select pin is active low. For the DAC8803, only the last 16 bits clocked into the serial register
are interrogated when the CS pin returns to the logic high state.
Since most microcontrollers output serial data in 8-bit bytes, two right-justified data bytes can be written to the
DAC8803. Keeping the CS line low between the first and second byte transfers results in a successful serial
register update.
18
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