Datasheet

www.ti.com
PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
DGND
DAC8802
(TOP VIEW)
A
GND
A
I
OUT
A
V
REF
A
R
FB
A
R
FB
B
V
REF
B
I
OUT
B
A
GND
B
LDAC
MSB
RS
V
DD
CS
CLK
SDI
DAC8802
SBAS351B – AUGUST 2005 – REVISED FEBRUARY 2007
PIN DESCRIPTION
PIN NAME DESCRIPTION
1 R
FB
A Establish voltage output for DAC A by connecting to external amplifier output.
2 V
REF
A DAC A Reference voltage input terminal. Establishes DAC A full-scale output voltage. Can be tied to V
DD
pin.
3 I
OUT
A DAC A Current output.
4 A
GND
A DAC A Analog ground.
5 A
GND
B DAC B Analog ground.
6 I
OUT
B DAC B Current output.
7 V
REF
B DAC B Reference voltage input terminal. Establishes DAC B full-scale output voltage. Can be tied to V
DD
pin.
8 R
FB
B Establish voltage output for DAC B by connecting to external amplifier output.
9 SDI Serial data input; data loads directly into the shift register.
Reset pin; active low input. Input registers and DAC registers are set to all 0s or midscale. Register data =
10 RS
0x0000 when MSB = 0. Register data = 0x2000 when MSB = 1 for DAC8802.
Chip-select; active low input. Disables shift register loading when high. Transfers serial register data to input
11 CS
register when CS goes high. Does not affect LDAC operation.
12 DGND Digital ground.
13 V
DD
Positive power-supply input. Specified range of operation is 2.7 V to 5.5 V.
MSB bit sets output to either 0 or midscale during a RESET pulse ( RS) or at system power-on. Output equals
14 MSB
zero scale when MSB = 0 and midscale when MSB = 1. MSB pin can be permanently tied to ground or V
DD
.
Load DAC register strobe; level sensitive active low. Transfers all input register data to the DAC registers.
15 LDAC
Asynchronous active low input. See Table 2 for operation.
16 CLK Clock input. Positive edge clocks data into shift register.
5
Submit Documentation Feedback