Datasheet

DAC8734
SBAS465A MAY 2009 REVISED SEPTEMBER 2009 ..................................................................................................................................................
www.ti.com
Zero Register n (where n = 0, 1, 2, or 3). Default = 0000h.
The Zero Register stores the user-calibration data that are used to eliminate the offset error. The data are nine
bits wide, 0.125 LSB/step, and the total adjustment is typically 32 LSB to +31.875 LSB, or ± 0.0488% of
full-scale range. The Zero Register uses a twos complement data format in both bipolar and unipolar modes of
operation.
Table 9. Zero Register
DB15:DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Reserved
(1)
Z8 Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0
(1) Writing to a reserved bit has no effect; reading the bit returns ' 0 ' .
Z8:Z0 OFFSET BITS ZERO ADJUSTMENT
011111111 +31.875 LSB
011111110 +31.750 LSB
000000001 +0.125 LSB
000000000 0 LSB (default)
111111111 0.125 LSB
100000001 31.875 LSB
100000000 32 LSB
Gain Register n (where n = 0, 1, 2, or 3). Default = 0000h.
The Gain Register stores the user-calibration data that are used to eliminate the gain error. The data are eight
bits wide, 1 LSB/step, and the total adjustment is typically 128 LSB to +127 LSB, or ± 0.195% of full-scale
range. The Gain Register uses a twos complement data format in both bipolar and unipolar modes of operation.
Table 10. Gain Register
DB15:DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Reserved
(1)
G7 G6 G5 G4 G3 G2 G1 G0
(1) Writing to a reserved bit has no effect; reading the bit returns ' 0 ' .
G7:G0 GAIN-CODE BITS GAIN ADJUSTMENT
01111111 +127 LSB
01111110 +126 LSB
00000001 +1 LSB
00000000 0 LSB (default)
11111111 1 LSB
10000001 127 LSB
10000000 128 LSB
28 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DAC8734