Datasheet

DAC8728
SBAS466A JUNE 2009REVISED NOVEMBER 2009
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Monitor Register (default = 0000h).
The Monitor Register selects one of the DAC outputs, reference buffer outputs, or offset DAC outputs to be
monitored through the V
MON
pin. Only one bit at a time can be set to '1'. When bits [D15:D4] = '0', the monitor is
disabled and V
MON
is in a Hi-Z state.
Note that if any value is written other than those specified in Table 12, the Monitor Register stores the invalid
value; however, the V
MON
pin is forced into a Hi-Z state.
Table 12. Monitor Register (Default = 0000h)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3:D0 V
MON
CONNECTS TO
0 0 0 0 0 0 0 0 0 0 0 1 X
(1)
Reference buffer B output
0 0 0 0 0 0 0 0 0 0 1 0 X Reference buffer A output
0 0 0 0 0 0 0 0 0 1 0 0 X Offset DAC B output
0 0 0 0 0 0 0 0 1 0 0 0 X Offset DAC A output
0 0 0 0 0 0 0 1 0 0 0 0 X DAC-0
0 0 0 0 0 0 1 0 0 0 0 0 X DAC-1
0 0 0 0 0 1 0 0 0 0 0 0 X DAC-2
0 0 0 0 1 0 0 0 0 0 0 0 X DAC-4
0 0 0 1 0 0 0 0 0 0 0 0 X DAC-4
0 0 1 0 0 0 0 0 0 0 0 0 X DAC-5
0 1 0 0 0 0 0 0 0 0 0 0 X DAC-6
1 0 0 0 0 0 0 0 0 0 0 0 X DAC-7
0 0 0 0 0 0 0 0 0 0 0 0 X Monitor function disabled, Hi-Z (default)
All other codes Monitor function disabled, Hi-Z
(1) X = don't care. Writing to this bit has no effect; reading the bit returns '0'.
Input Data Register for DAC-n (where n = 0 to 7). Default = 0000h.
This register stores the DAC data written to the device when the SCE bit = '1'. When the SCE bit = '0' (default),
the DAC Data Register stores the DAC data written to the device. When the data are loaded into the
corresponding DAC latch, the DAC output changes to the new level defined by the DAC data. The default value
after power-on or reset is 0000h.
Table 13. DAC-n
(1)
Input Data Register
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DB15
(2)
DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(1) n = 0, 1, 2, 3, 4, 5, 6, or 7.
(2) DB15:DB0 are the DAC data bits
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