Datasheet
DAC8728
SBAS466A –JUNE 2009–REVISED NOVEMBER 2009
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PARALLEL INTERFACE
The DAC8728 interfaces with microprocessors using a 16-bit data bus. The interface is double-buffered, allowing
simultaneous updating of all DACs. Each DAC has an input data register, DAC data register, user-calibration
gain register, user-calibration zero register, and DAC latch. When user calibration is enabled, the input data
register receives data from the data bus, the DAC Data Register stores the data after internal calibration, and the
DAC latch sets the analog output level. When user calibration is disabled (default), the DAC data register stores
data from the data bus, and the DAC latch sets the analog output level. Five address lines (A0:A4) select which
DAC or auxiliary register is addressed. Table 10 shows the register map.
Table 10. Register Map
ADDRESS BITS DATA BITS
A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3:D0 REGISTER
Configuration
0 0 0 0 0 A/B LD RST PD-A PD-B SCE GBF GAIN-A GAIN-B Don't Care
(1)
Register
Ref Ref
DAC- DAC- DAC- DAC- DAC- DAC- DAC- Offset Offset Don't
0 0 0 0 1 DAC-0 Buffer Buffer Monitor Register
7 6 5 4 3 2 1 DAC-A DAC-B Care
(1)
-A -B
0 0 0 1 0 GPIO Don't Care
(1)
GPIO Register
Offset DAC-A
0 0 0 1 1 D15:D0, default = 39322 (999Ah)
Data Register
Offset DAC-B
0 0 1 0 0 D15:D0 , default = 39322 (999Ah)
Data Register
Busy Flag
0 0 1 0 1 BF-7 BF-6 BF-5 BF-4 BF-3 BF-2 BF-1 BF-0 Don't Care
(1)
Register
0 0 1 1 0 Reserved
(2)
Reserved
0 0 1 1 1 Reserved
(2)
Reserved
0 1 0 0 0 DB15:DB0 DAC-0
0 1 0 0 1 DB15:DB0 DAC-1
0 1 0 1 0 DB15:DB0 DAC-2
0 1 0 1 1 DB15:DB0 DAC-3
0 1 1 0 0 DB15:DB0 DAC-4
0 1 1 0 1 DB15:DB0 DAC-5
0 1 1 1 0 DB15:DB0 DAC-6
0 1 1 1 1 DB15:DB0 DAC-7
1 0 0 0 0 Z15:Z0, default = 0 (0000h), twos complement Zero Register-0
1 1 0 0 0 G15:G0, default = 32768 (8000h), straight binary Gain Register-0
1 0 0 0 1 Z15:Z0, default = 0 (0000h), twos complement Zero Register-1
1 1 0 0 1 G15:G0, default = 32768 (8000h), straight binary Gain Register-1
1 0 0 1 0 Z15:Z0, default = 0 (0000h), twos complement Zero Register-2
1 1 0 1 0 G15:G0, default = 32768 (8000h), straight binary Gain Register-2
1 0 0 1 1 Z15:Z0, default = 0 (0000h), twos complement Zero Register-3
1 1 0 1 1 G15:G0, default = 32768 (8000h), straight binary Gain Register-3
1 0 1 0 0 Z15:Z0, default = 0 (0000h), twos complement Zero Register-4
1 1 1 0 0 G15:G0, default = 32768 (8000h), straight binary Gain Register-4
1 0 1 0 1 Z15:Z0, default = 0 (0000h), twos complement Zero Register-5
1 1 1 0 1 G15:G0, default = 32768 (8000h), straight binary Gain Register-5
1 0 1 1 0 Z15:Z0, default = 0 (0000h), twos complement Zero Register-6
1 1 1 1 0 G15:G0, default = 32768 (8000h), straight binary Gain Register-6
1 0 1 1 1 Z15:Z0, default = 0 (0000h), twos complement Zero Register-7
1 1 1 1 1 G15:G0, default = 32768 (8000h), straight binary Gain Register-7
(1) Writing to a Don't Care bit has no effect; reading the bit returns '0'.
(2) Writing to a reserved bit has no effect; reading the bit returns '0'.
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