Datasheet
DAC8728
SBAS466A –JUNE 2009–REVISED NOVEMBER 2009
www.ti.com
ELECTRICAL CHARACTERISTICS: Dual-Supply (continued)
All specifications at T
A
= T
MIN
to T
MAX
, AV
DD
= +16.5V, AV
SS
= –16.5V, DV
DD
= +5V, REF-A and REF-B = +5V, gain = 6,
AGND-x = DGND = 0V, and Offset DAC A and Offset DAC B are at default values
(1)
, unless otherwise noted.
DAC8728
PARAMETER CONDITIONS MIN TYP MAX UNIT
ANALOG OUTPUT (V
OUT
-0 to V
OUT
-7)
(3)
V
REF
= +5V –15 +15 V
Voltage output
(4)
V
REF
= +1.5V –4.5 +4.5 V
Output impedance Code = 8000h 0.5 Ω
Short-circuit current
(5)
±10 mA
Load current See Figure 37 ±3 mA
T
A
= +25°C, device operating for 500 hours, full-scale output 3.4 ppm of FSR
Output drift vs time
T
A
= +25°C, device operating for 1000 hours, full-scale output 4.3 ppm of FSR
Capacitive load stability 500 pF
To 0.03% of FSR, C
L
= 200pF, R
L
= 10kΩ, code from 0000h
10 μs
to FFFFh and FFFFh to 0000h
To 1 LSB, C
L
= 200pF, R
L
= 10kΩ, code from 0000h to
Settling time 15 μs
FFFFh and FFFFh to 0000h
To 1 LSB, C
L
= 200pF, R
L
= 10kΩ, code from 7F00h to
6 μs
8100h and 8100h to 7F00h
Slew rate
(6)
6 V/μs
Power-on delay
(7)
From IOV
DD
≥ +1.8V and DV
DD
≥ +2.7V to CS low 200 μs
Power-down recovery time 50 μs
Digital-to-analog glitch
(8)
Code from 7FFFh to 8000h and 8000h to 7FFFh 4 nV-s
Glitch impulse peak amplitude Code from 7FFFh to 8000h and 8000h to 7FFFh 5 mV
Channel-to-channel isolation
(9)
V
REF
= 4V
PP
, f = 1kHz 88 dB
DACs in the same group 10 nV-s
DAC-to-DAC crosstalk
(10)
DACs among different groups 1 nV-s
Digital crosstalk
(11)
1 nV-s
Digital feedthrough
(12)
1 nV-s
T
A
= +25°C at 10kHz, gain = 6 200 nV/√Hz
Output noise T
A
= +25°C at 10kHz, gain = 4 130 nV/√Hz
0.1Hz to 10Hz, gain = 6 20 μV
PP
Power-supply rejection
(13)
AV
DD
= ±15.5V to ±16.5V 0.05 LSB
(3) Specified by design.
(4) The analog output range of V
OUT
-0 to V
OUT
-7 is equal to (6 × V
REF
– 5 × OUTPUT_OFFSET_DAC) for gain = 6. The maximum value of
the analog output must not be greater than (AV
DD
– 0.5V), and the minimum value must not be less than (AV
SS
+ 0.5V). All
specifications are for a ±16.5V power supply and a ±15V output, unless otherwise noted.
(5) When the output current is greater than the specification, the current is clamped at the specified maximum value.
(6) Slew rate is measured from 10% to 90% of the transition when the output changes from 0 to full-scale.
(7) Power-on delay is defined as the time from when the supply voltages reach the specified conditions to when CS goes low, for valid
digital communication.
(8) Digital-to-analog glitch is defined as the amount of energy injected into the analog output at the major code transition. It is specified as
the area of the glitch in nV-s. It is measured by toggling the DAC register data between 7FFFh and 8000h in straight binary format.
(9) Channel-to-channel isolation refers to the ratio of the signal amplitude at the output of one DAC channel to the amplitude of the
sinusoidal signal on the reference input of another DAC channel. It is expressed in dB and measured at midscale.
(10) DAC-to-DAC crosstalk is the glitch impulse that appears at the output of one DAC as a result of both the full-scale digital code and
subsequent analog output change at another DAC. It is measured with LDAC tied low and expressed in nV-s.
(11) Digital crosstalk is the glitch impulse transferred to the output of one converter as a result of a full-scale code change in the DAC input
register of another converter. It is measured when the DAC output is not updated, and is expressed in nV-s.
(12) Digital feedthrough is the glitch impulse injected to the output of a DAC as a result of a digital code change in the DAC input register of
the same DAC. It is measured with the full-scale digital code change without updating the DAC output, and is expressed in nV-s.
(13) The output must not be greater than (AV
DD
– 0.5V) and not less than (AV
SS
+ 0.5V).
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