Datasheet

DAC8728
www.ti.com SBAS466A –JUNE 2009–REVISED NOVEMBER 2009
POWER-ON RESET
The DAC8728 contains a power-on reset circuit that controls the output during power-on and power down. This
feature is useful in applications where the known state of the DAC output during power-on is important. The
Offset DAC Registers, DAC Data Registers, and DAC latches are loaded with the value defined by the RSTSEL
pin, as shown in Table 8. The Gain Registers and Zero Registers are loaded with default values. The Input Data
Register is reset to 0000h, independent of the RSTSEL state.
Table 8. Bipolar Output Reset Values for Dual Power-Supply Operation
VALUE OF DAC VALUE OF OFFSET
DATA REGISTER DAC REGISTER
RSTSEL PIN USB/BTC PIN INPUT FORMAT AND DAC LATCH FOR GAIN = 6
(1)
V
OUT
DGND DGND Straight Binary 0000h 999Ah –Full-Scale
IOV
DD
DGND Straight Binary 8000h 999Ah 0 V
DGND IOV
DD
Twos Complement 8000h 199Ah –Full-Scale
IOV
DD
IOV
DD
Twos Complement 0000h 199Ah 0 V
(1) Offset DAC A and Offset DAC B are trimmed in manufacturing to minimize the error for symmetrical output. The default value may vary
no more than ±10 LSB from the nominal number listed in this table.
In single-supply operation, the Offset DAC is turned off and the output is unipolar. The power-on reset is defined
as shown in Table 9.
Table 9. Unipolar Output Reset Values for Single Power-Supply Operation
VALUE OF DAC DATA
REGISTER AND DAC
RSTSEL PIN USB/BTC PIN INPUT FORMAT LATCH V
OUT
DGND DGND Straight Binary 0000h 0 V
IOV
DD
DGND Straight Binary 8000h Midscale
DGND IOV
DD
Twos Complement 8000h 0 V
IOV
DD
IOV
DD
Twos Complement 0000h Midscale
HARDWARE RESET
When the RST pin is low, the device is in hardware reset. All the analog outputs (V
OUT
-0 to V
OUT
-7), the DAC
registers, and the DAC latches are set to the reset values defined by the RSTSEL pin as shown in Table 8 and
Table 9. In addition, the Gain and Zero registers are loaded with default values, communication is disabled, and
the signals on R/W, CS , [D0:D15], and [A0:A4] are ignored (note that [D0:D15] are in a high-impedance state).
The Input Data Register is reset to 0000h, independent of the RSTSEL state. On the rising edge of RST, the
analog outputs (V
OUT
-0 to V
OUT
-7) maintain the reset value as defined by the RSTSEL pin until a new value is
programmed. After RST goes high, the parallel interface returns to normal operation. CS must be set to a logic
high whenever RST is used.
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