Datasheet

DAC8728
SBAS466A –JUNE 2009–REVISED NOVEMBER 2009 www.ti.com
TIMING CHARACTERISTICS
(1) (2) (3) (4) (5)
At –40°C to +105°C, DV
DD
= +3V to +5V, and IOV
DD
= +3V, unless otherwise noted.
PARAMETER MIN MAX UNIT
t
1
CS width for write operation 25 ns
t
2
Delay from R/W falling edge to CS falling edge 2 ns
t
3
Delay from CS rising edge to R/W rising edge 2 ns
t
4
Delay from address valid to CS falling edge 6 ns
t
5
Delay from CS rising edge to address change 0 ns
t
6
Delay from data valid to CS rising edge 25 ns
t
7
Delay from CS rising to data change 5 ns
t
8
CS width for read operation 50 ns
t
9
Delay from R/W rising edge to CS falling edge 2 ns
t
10
Delay from CS rising edge to R/W falling edge 2 ns
t
11
Delay from address valid to CS falling edge 6 ns
t
12
Delay from CS rising to address change 0 ns
t
13
Delay from CS falling edge to data valid 40 ns
t
14
Delay from CS rising to data bus off (Hi-Z) 2 ns
t
15
Delay from CS rising edge to LDAC falling edge 5 ns
t
16
LDAC pulse width 10 ns
t
17
Delay from LDAC rising edge to next CS rising edge 20 ns
t
18
Delay from BUSY rising edge to next LDAC falling edge 0 ns
t
19
Delay from CS rising edge to next LDAC falling edge 30 ns
t
20
Delay from CS rising edge to BUSY falling edge 20 ns
t
21
Delay from LDAC falling edge to BUSY rising edge 50 ns
(1) Specified by design; not production tested.
(2) Sample tested during the initial release and after any redesign or process changes that may affect these parameters.
(3) Rise and fall times of all digital input signals are 5ns.
(4) Rise and fall times of all digital outputs are 5ns for a 10pF capacitor load.
(5) For sequential writes to the same address, there must be a minimum of 50ns between the CS rising edges.
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