Datasheet

t
11
t
12
t
13
Hi-Z Hi-Z
t
14
t
9
t
10
t
8
CS
R/W
A4:A0
D15:D0
t
4
t
6
t
5
Hi-Z Hi-Z
t
7
t
2
t
3
t
1
CS
R/W
A4:A0
D15:D0
WriteOperation1:
1.WritingtotheConfigurationRegister,OffsetRegister,
MonitorRegister,GPIORegister.
2.WritingtotheDACInputRegisters,ZeroRegisters,and
GainRegistersinAsynchronousmode( pinistiedlow).LDAC
t
4
t
6
t
15
t
5
Hi-Z Hi-Z
t
7
t
2
t
3
t
1
CS
R/W
LDAC
LDbitcanbesettoreplace LDAC
toupdatetheDACoutput
WriteOperation2:
WritingtotheDACInputDataRegisters,ZeroRegisters,and
GainRegisterswhenthecorrectionengineisdisabledand
DACoutputsareupdatedinSynchronousmode.
A4:A0
D15:D0
t
16
CS
LDbitcanbesettoreplace LDAC
toupdatetheDACoutput
WriteOperation3:
WritingtotheDACInputDataRegisters,ZeroRegisters,andGainRegisterswhen thecorrectionengineis
enabled(SCE=1)andtheDACoutputsareupdatedinSynchronousmode.Theupdatetrigger(either LDAC
ortheLDbit)activatesafterthecorrectioncompletes.
t
18
t
17
BUSY
LDAC
t
16
DAC8728
SBAS466A –JUNE 2009–REVISED NOVEMBER 2009 www.ti.com
TIMING DIAGRAMS
Figure 2. Read Operation
Figure 3. Write Operation 1
space
Figure 4. Write Operation 2
Figure 5. Write Operation 3
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