Datasheet

DAC8728
www.ti.com SBAS466A –JUNE 2009–REVISED NOVEMBER 2009
PIN DESCRIPTIONS (continued)
PIN NO.
PIN
NAME
QFN-56 TQFP-64 I/O DESCRIPTION
Load DAC latch control input (active low). When LDAC is low, the DAC latch is transparent and the
contents of the DAC Data Register are transferred to it. The DAC output changes to the corresponding
LDAC 17 18 I level simultaneously when the DAC latch is updated. See the DAC Output Update section for details. If
asynchronous mode is desired, LDAC must be permanently tied low before power is applied to the
device. If synchronous mode is desired, LDAC must be logic high during power-on.
Reset input (active low). Logic low on this pin resets the DAC registers and DACs to the values defined
RST 18 19 I
by the RSTSEL pin. CS must be at logic high when RST is used.
A0 19 20 I Address bit A0 to specify the internal registers.
A1 20 21 I Address bit A1 to specify the internal registers.
DV
DD
21 24 I Digital power supply
DGND 22 25 I Digital ground
A2 23 26 I Address bit A2 to specify the internal registers.
A3 24 27 I Address bit A3 to specify the internal registers.
A4 25 29 I Address bit A4 to specify the internal registers.
DGND 26 30 I Digital ground
General-purpose digital input/output. This pin is a bidirectional, open-drain, digital input/output, and
GPIO 27 33 I/O
requires an external pullup resistor. See the GPIO Pin section for details.
Output reset selection. Selects the output voltage on the V
OUT
pin after power-on or hardware reset.
RSTSEL 28 34 I
Refer to the Power-On Reset section for details.
V
OUT
-7 29 36 O DAC-7 output
OFFSET DAC-B analog output. Must be connected to AGND-B during single-supply operation
OFFSET-B 30 37 O
(AV
SS
= 0V). This pin is not intended to drive an external load.
AV
SS
31 38 I Negative analog power supply. Connect to AGND in single-supply operation.
V
OUT
-6 32 39 O DAC-6 output
AGND-B 33 40 I Group B
(2)
analog ground and the ground of REF-B. This pin must be tied to AGND-A and DGND.
AV
DD
34 41 I Positive analog power supply
V
OUT
-5 35 42 O DAC-5 output
REF-B 36 43 I Group B
(2)
reference input
V
OUT
-4 37 44 O DAC-4 output
14, 22, 23,
NC 38 28, 31, 32, — Not connected
35, 45, 53
D0 39 46 I/O Data bit 0
D1 40 47 I/O Data bit 1
D2 41 48 I/O Data bit 2
D3 42 49 I/O Data bit 3
D4 43 50 I/O Data bit 4
D5 44 51 I/O Data bit 5
D6 45 52 I/O Data bit 6
DGND 46 54 I Digital ground
IOV
DD
47 55 I Digital interface power supply
DV
DD
48 56 I Digital power supply
R/W 49 57 I Read and write signal. High for reading operation; low for writing operation.
CS 50 58 I Chip select input (active low)
D7 51 59 I/O Data bit 7
D8 52 60 I/O Data bit 8
D9 53 61 I/O Data bit 9
D10 54 62 I/O Data bit 10
D11 55 63 I/O Data bit 11
D12 56 64 I/O Data bit 12
(2) Group A consists of DAC-0, DAC-1, DAC-2, and DAC-3. Group B consists of DAC-4, DAC-5, DAC-6, and DAC-7.
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