Datasheet

www.ti.com Analog Interface
2 Analog Interface
For maximum flexibility, the DAC8718EVM can interface to multiple analog sources. Samtec part numbers
SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provides a 10-pin, dual-row, header at J1. This header
provides access to the analog input and output pins of the DAC. An additional connector, J4, and test
points are added to the evaluation module to allow access to all of the analog pins on the DAC. Consult
Samtec at http://www.samtec.com or call 1-800-SAMTEC-9 for a variety of mating connector options.
Table 1 summarizes the pinouts for analog interface J1.
Table 1. J1: Analog Interface Pinout
Pin Number Signal Description
J1.2 V
OUT
-0 Analog output 0
J1.4 V
OUT
-1 Analog output 1
J1.6 V
OUT
-2 Analog output 2
J1.8 V
OUT
-3 Analog output 3
J1.10 V
OUT
-4 Analog output 4
J1.12 V
OUT
-5 Analog output 5
J1.14 V
OUT
-6 Analog output 6
J1.16 V
OUT
-7 Analog output 7
J1.18 EXT-REFA External reference source input
for REF-A (V
OUT
-0 to V
OUT
-3)
J1.20 EXT-REFB External reference source input
for REF-B (V
OUT
-4 to V
OUT
-7)
J1.1-1.19 (odd) GND Analog ground connection
Table 2 summarizes the pinouts for analog interface J4.
Table 2. J4: Analog AIN Interface Pinout
Pin Number Signal Description
J4.2 AIN-0 Analog input 0
J4.4 AIN-1 Analog input 1
J4.1 and J1.3 GND Analog ground connection
The analog interface is populated on the top and the bottom of the evaluation model. All of the output pins
and the AIN-x pins are routed directly from the DAC8718 to the connector.
The GND pins of the DAC8718 are connected directly to the ground of the EVM board.
The DAC8718 has two auxiliary analog input pins, A
IN
-0 and A
IN
-1. These signals can be relayed to the
V
MON
output pin. Care must be taken to avoid overvoltage on these input pins. Make sure that the analog
inputs do not exceed the Absolute Maximum Ratings found in the DAC8718 data sheet. The two A
IN
pins
can be accessed from the J4 header; see Table 2.
The DAC8718EVM has two external reference voltage options. J1.18 controls the external reference
voltage for the REF-A input. J1.20 controls the reference for the REF-B input. When an external reference
is used, jumpers JP1-JP4 must be configured properly. Test points TP3 and TP4 can be used to verify
that the jumpers are configured properly and the correct reference voltage is applied to the DAC.
The output of the DAC8718 internal offset DAC is routed to test points TP5 and TP6. Jumpers JP6 and
JP7 must be properly configured to route the OFFSET-A (TP5) and OFFSET-B (TP6) signals to the test
points.
The V
MON
output allows the user to relay any of the DAC outputs, as well as A
IN
-0 or A
IN
-1, to a single pin.
V
MON
is routed to test point TP11 and is connected to a 0.1μF capacitor.
3
SBAU158A–February 2010–Revised May 2011 DAC8718EVM
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