Datasheet

SCLK
t
Lead
t
wsck
t
wsck
t
r
t
f
-- Don’tCare
BIT-14
BIT-13, …, 1BIT-15 (MSB) BIT-0
SDIN
t
hi
t
su
DACUpdated
t
UPDAC
1st
2nd 15th 16th
t
td
CS
t
sck
t
WAIT
DAC8581
www.ti.com SLAS481C –AUGUST 2005–REVISED OCTOBER 2012
TIMING REQUIREMENTS
(1)
PARAMETER MIN MAX UNIT
t
SCK
SCLK period 20 ns
t
WSCK
SCLK high or low time 10 ns
t
Lead
Delay from falling CS to first rising SCLK 20 ns
t
TD
CS High between two active Periods 20 ns
t
SU
Data setup time (Input) 5 ns
t
H
I Data hold time (input) 5 ns
t
R
Rise time 30 ns
t
F
Fall time 30 ns
t
WAIT
Delay from 16th falling edge of SCLK to CS low 100 ns
t
UPDAC
Delay from 16th falling edge of SCLK to DAC output 1 μs
V
DD
High to CS Low (power-up delay) 100 μs
(1) Assured by design. Not production tested.
Figure 1. DAC8581 Timing Diagram
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