Datasheet

I0 +

I1 ) (I2 * I1)(D0 * VI1)

VI2 * VI1

VI1

VI0

VI2

Main−

DACTransferCurve

VI0B

PWL Segment

I0B

Ideal−

DACTransferCurve

DAC8581

SLAS481C –AUGUST 2005–REVISED OCTOBER 2012

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Figure 21. The Geometry Behind the PWL Calibration

(1)

Where both x-axis and y-axis are normalized from 0 to 65535, and:

VI0: Desired ideal DAC voltage corresponding to input code D0.

VI0B: DAC8581 output voltage, which approximates VI0 after PWL calibration. This is the actual DAC8581

output for input code D0 after PWL calibration.

I0: DAC8581 code generating VI0B, an approximation to the desired voltage VI0. This is actual code

loaded into DAC latch for input code D0, after PWL calibration.

I0B: DAC8581 code, which generates output VI0. This code is approximated by the N-segment PWL

calibration.

I1: Contents of memory COEFF[], addressed by the 10 MSBs of user input code D0.

I2: Contents of the next memory location in COEFF[].

VI1: DAC8581 output voltage corresponding to code I1. Notice that (D0–VI1) is nothing but the six LSBs of

the input code D0, given that the y-axis is normalized from 0 to 65,536.

VI2: DAC8581 output voltage corresponding to code I2. Notice that (VI2–VI1) is always equal to number 64,

given that the y-axis is normalized from 0 to 65,536. Division becomes a 6-bit arithmetic right shift.

Other similar PWL calibration implementations exist. This particular algorithm does not need digital division, and

it does not accumulate measurement errors at each segment.

Product Folder Links: DAC8581