Datasheet

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I
2
C High Speed Examples (A0, A1, A2, A3 and LDAC pins tied to GND):
LAYOUT
DAC8574
SLAS377B JANUARY 2003 REVISED DECEMBER 2004
EXAMPLE 22: Ramp generation on channel D (Up to Code 7 is shown)
HS Master Code NOT REPEATED ADDRESS C [7 0]
START 0000 1000 ACK START 10011 0000 ACK 0001 0110 ACK
Previous VoutD voltage valid
MSB [7 0] LSB [7 0] MSB [7 0] LSB [7 0]
0000 0000 ACK 0000 0000 ACK 0000 0000 ACK 0000 0001 ACK
Previous VoutD voltage valid VoutD = 0 V VoutD = 76 µV
MSB [7 0]] LSB [7 0] MSB 7 0] LSB [7 0]
0000 0000 ACK 0000 0010 ACK 0000 0000 ACK 0000 0011 ACK
VoutD = 76 µV VoutD = 2 x 76 µV VoutD = 3 x 76
µV
MSB [7 0] LSB [7 0] MSB [7 0] LSB [7 0]
0000 0000 ACK 0000 0100 ACK 0000 0000 ACK 0000 0101 ACK
VoutD = 3 x 76 µV VoutD = 4 x 76 µV VoutD = 5 x 76
µV
MSB [7 0] LSB [7 0] MSB [7 0] LSB [7 0]
0000 0000 ACK 0000 0110 ACK 0000 0000 ACK 0000 0111 ACK
VoutD = 5 x 76 µV VoutD = 6 x 76 µV VoutD = 7 x 76
µV
A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power
supplies.
The power applied to V
DD
should be well-regulated and low noise. Switching power supplies and dc/dc
converters often have high-frequency glitches or spikes riding on the output voltage. In addition, digital
components can create similar high-frequency spikes as their internal logic switches states. This noise can easily
couple into the DAC output voltage through various paths between the power connections and analog output.
As with the GND connection, V
DD
should be connected to a positive power-supply plane or trace that is separate
from the connection for digital logic until they are connected at the power-entry point. In addition, a 1 µF to 10 µF
capacitor in parallel with a 0.1 µF bypass capacitor is strongly recommended. In some situations, additional
bypassing may be required, such as a 100 µF electrolytic capacitor or even a Pi filter made up of inductors and
capacitors—all designed to essentially low-pass filter the –5 V supply, removing the high-frequency noise.
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