Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) TSSOP 16

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FEATURES DESCRIPTION

APPLICATIONS

Resistor

Network

Data

Buffer A

DAC

Data

Buffer D

DAC

DAC A

DAC D

Buffer

Control

Power-Down

Control Logic

OUT

REF

A0 A1 A2

GND

C Block

SCL

SDA

LDAC

REF

IOV

DAC8574

SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004

QUAD, 16-BIT, LOW-POWER, VOLTAGE OUTPUT,

C INTERFACE DIGITAL-TO-ANALOG CONVERTER

• Micropower Operation: 950 µA at 5 V V

The DAC8574 is a low-power, quad channel, 16-bit

• Power-On Reset to Zero

buffered voltage output DAC. Its on-chip precision

output amplifier allows rail-to-rail output swing to be

• +2.7-V to +5.5-V Analog Power Supply

achieved. The DAC8574 utilizes an I

C compatible

• 16-Bit Monotonic

two wire serial interface supporting high-speed

• Settling Time: 10µs to ± 0.003% FSR

interface mode with address support of up to sixteen

• I

C™ Interface Up to 3.4 Mbps

DAC8574s for a total of 64 channels on the bus.

• Data Transmit Capability

The DAC8574 requires an external reference voltage

• On-Chip Output Buffer Amplifier, Rail-to-Rail

to set the output range of the DAC. The DAC8574

Operation

incorporates a power-on-reset circuit that ensures

• Double-Buffered Input Register

that the DAC output powers up at zero volts and

remains there until a valid write takes place to the

• Address Support for up to Sixteen DAC8574s

device. The DAC8574 contains a power-down fea-

• Synchronous Update Support for up to 64

ture, accessed via the internal control register, that

Channels

reduces the current consumption of the device to 200

• Operation From –40 ° C to 105 ° C

nA at 5 V.

• Small 16-Lead TSSOP Package

The low power consumption of this part in normal

operation makes it ideally suited to portable battery

operated equipment. The power consumption is less

• Process Control

than 5 mW at V

= 5 V reducing to 1 µW in

power-down mode.

• Data Acquisition Systems

• Closed-Loop Servo Control

The DAC8574 is available in a 16-lead TSSOP

• PC Peripherals

package.

• Portable Instrumentation

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

C is a trademark of Philips Corporation.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (45 pages)

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DAC 8534 ® DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 QUAD, 16-BIT, LOW-POWER, VOLTAGE OUTPUT, I C INTERFACE DIGITAL-TO-ANALOG CONVERTER 2 FEATURES • • • • • • • • • • • • • DESCRIPTION Micropower Operation: 950 µA at 5 V VDD Power-On Reset to Zero +2.7-V to +5.5-V Analog Power Supply 16-Bit Monotonic Settling Time: 10µs to ±0.003% FSR I2C™ Interface Up to 3.
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 ELECTRICAL CHARACTERISTICS VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications -40°C to +105°C, unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE (1) (2) Resolution 16 Bits Relative accuracy Differential nonlinearity Specified monotonic by design Zero-scale error 5 Full-scale error -0.
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 ELECTRICAL CHARACTERISTICS (continued) VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications -40°C to +105°C, unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS IDD (all power-down modes) IDD@ VDD=+3.6V to +5.5V VIH= IOVDDand IOVIL=GND 0.2 1 µA IDD@ VDD =+2.7V to +3.6V VIH= VDDand VIL=GND 0.
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 TIMING CHARACTERISTICS (continued) VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; all specifications -40°C to +105°C, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN MAX UNITS 1000 ns 300 ns 10 80 ns 20 160 ns 300 ns Standard mode tRCL1 Rise time of SCL signal after a Fast mode repeated START condition and after an acknowledge BIT High-speed mode, CB = 100 pF max High-speed mode, CB = 400 pF max 20 + 0.
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS At TA = +25°C, unless otherwise noted. 64 48 32 16 0 - 16 - 32 - 48 - 64 Channel A V DD = 5 V LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE LE - LSB LE - LSB LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE DLE - LSB 0 - 0.5 0 - 0.5 Digital Input Code Digital Input Code 64 48 32 16 0 - 16 - 32 - 48 - 64 Figure 1. Figure 2.
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. 64 48 32 16 0 - 16 - 32 - 48 - 64 Channel C VDD = 2.7 V LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE LE - LSB LE - LSB LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 0.5 0 - 0.5 VDD = 2.7 V 0.5 0 - 0.
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. PULLDOWN CAPABILITY vs SINK CURRENT PULLDOWN CAPABILITY vs SINK CURRENT 0.15 0.15 Channel B 0.125 VOUT - Output Voltage - V VOUT - Output Voltage - V Channel A V DD = 2.7 V 0.1 0.075 VDD = 5 V 0.05 VREF = VDD - 10 mV 0.025 DAC Loaded With 0000 0.125 0.1 V DD = 2.7 V 0.075 VDD = 5 V 0.05 VREF = VDD - 10 mV 0.
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. PULLUP CAPABILITY vs SOURCE CURRENT PULLUP CAPABILITY vs SOURCE CURRENT 5 5 Channel D VOUT - Output Voltage - V VOUT - Output Voltage - V Channel C 4.95 4.9 VREF = VDD - 10 mV DAC Loaded With FFFF H 4.85 4.95 4.9 VREF = VDD - 10 mV DAC Loaded With FFFF H 4.85 VDD = 5 V VDD = 5 V 4.8 4.
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. SUPPLY CURRENT vs DIGITAL INPUT CODE SUPPLY CURRENT vs TEMPERATURE 1200 1200 VDD = V REF = 5 V V DD = V REF = 5 V 1000 I DD - Supply Current -µ A I DD - Supply Current -µ A 1000 800 600 VDD = V REF = 2.
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. HISTOGRAM OF CURRENT CONSUMPTION HISTOGRAM OF CURRENT CONSUMPTION 1500 1500 V DD = V REF = 5 V Reference Current Included 1000 VDD = VREF = 2.7 V Reference Current Included I DD - Current Consumption - µA I DD VDD = VREF = 5 V Power- Up Code = FFFFH 2.52 2.51 VOUT (V, 10 mV/div) VOUT - Output Voltage - V 2.50 1060 1030 970 2.49 2.48 2.47 2.46 2.
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. FULL-SCALE SETTLING TIME (Large Signal) ABSOLUTE ERROR 6 10 Output Error - mV 6 4 Channel B Output Channel D Output 2 0 -2 -4 -6 -8 Channel A Output VDD = VREF = 5.5 V Output Loaded with 2 kΩ and 200 pF to GND 5 VOUT - Output Voltage - V VDD = VREF = 2.
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY 0 0 VDD = VREF = 5 V FS = 52 ksps, - 1 dB FSR Digital Input Measurement Bandwidth = 20 kHz - 30 - 40 THD - 50 - 60 - 70 - 80 3rd Harmonic - 90 VDD = VREF = 2.
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 THEORY OF OPERATION D/A SECTION The architecture of the DAC8574 consists of a string DAC followed by an output buffer amplifier. Figure 45 shows a generalized block diagram of the DAC architecture. VREFH 50 k 50 k 70 k _ Ref+ Resistor String Ref- DAC Register + VOUT VREFL Figure 45.
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 THEORY OF OPERATION (continued) The DAC8574 works as a slave and supports the following data transfer modes, as defined in the I2C-Bus Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (3.4 Mbps). The data transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as F/S-mode in this document.
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 THEORY OF OPERATION (continued) SDA SCL Data Line Stable; Data Valid Change of Data Allowed Figure 48. Bit Transfer on the I2C Bus Data Output by Transmitter Not Acknowledge Data Output by Receiver Acknowledge SCL From Master 1 2 8 9 S Clock Pulse for Acknowledgement START Condition Figure 49.
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 2 DAC8574 I C Update Sequence The DAC8574 requires a start condition, a valid I2C address, a control byte, an MSB byte, and an LSB byte for a single update. After the receipt of each byte, DAC8574 acknowledges by pulling the SDA line low during the high period of a single clock pulse. A valid I2C address selects the DAC8574. The control byte sets the operational mode of the selected DAC8574.
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 Broadcast Address Byte MSB LSB 1 0 0 1 0 0 0 0 Broadcast addressing is also supported by DAC8574. Broadcast addressing can be used for synchronously updating or powering down multiple DAC8574 devices. DAC8574 is designed to work with other members of the DAC857x and DAC757x families to support multichannel synchronous update. Using the broadcast address, DAC8574 responds regardless of the states of the address pins.
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 Table 2. Control Byte C7 C6 C5 C4 C3 C2 C1 C0 MSB7 MSB6 MSB5... A3 A2 Load1 Load0 Don't Care Ch Sel 1 Ch Sel 0 PD0 MSB (PD1) MSB-1 (PD2) MSB-2 ...
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 LDAC Functionality Depending on the control byte, DACs are synchronously updated on the falling edge of the acknowledge signal that follows LS byte. The LDAC pin is required only when an external timing signal is used to update all the channels of the DAC asynchronously. LDAC is a positive edge triggered asynchronous input that allows four DAC output voltages to be updated simultaneously with temporary register data.
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 DAC8574 as a Slave Receiver - High-Speed Mode Figure 52 shows the high-speed mode master transmitter addressing a DAC8574 Slave Receiver with a 7-bit address.
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 Master Transmitter Writing to a Slave Receiver (DAC8574) in Standard/Fast Modes All write access sequences begin with the device address (with R/W = 0) followed by the control byte. This control byte specifies the operation mode of DAC8574 and determines which channel of DAC8574 is being accessed in the subsequent read/write operation.
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 Master Transmitter Writing to a Slave Receiver (DAC8574) in HS Mode When writing data to the DAC8574 in HS-mode, the master begins to transmit what is called the HS-Master Code (0000 1XXX) in F/S-mode. No device is allowed to acknowledge the HS-Master Code, so the HS-Master Code is followed by a NOT acknowledge.
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 DAC8574 as a Slave Transmitter - Standard and Fast Mode Figure 53 shows the standard and fast mode master transmitter addressing a DAC8574 Slave Transmitter with a 7-bit address.
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 Master Receiver Reading From a Slave Transmitter (DAC8574) in Standard/Fast Modes When reading data back from the DAC8574, the user begins with an address byte (with R/W = 0) after which the DAC8574 will acknowledge by pulling SDA low. This address byte is usually followed by the Control Byte, which is also acknowledged by the DAC8574.
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 Master Receiver Reading From a Slave Transmitter (DAC8574) in HS-Mode When reading data to the DAC8574 in HS-MODE, the master begins to transmit, what is called the HS-Master Code (0000 1XXX) in F/S-mode. No device is allowed to acknowledge the HS-Master Code, so the HS-Master Code is followed by a NOT acknowledge.
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 Power-On Reset The DAC8574 contains a power-on-reset circuit that controls the output voltage during power up. On power up, the DAC register is filled with zeros and the output voltage is 0 V; it remains there until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC while it is in the process of powering up.
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DAC8574 SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 www.ti.com CURRENT CONSUMPTION The DAC8574 typically consumes 225 µA at VDD = 5 V and 200 µA at VDD = 3 V for each active channel, including reference current consumption. Additional current consumption can occur at the digital inputs if VIH << VDD. For most efficient power operation, CMOS logic levels are recommended at the digital inputs to the DAC. In power-down mode, typical current consumption is 200 nA.
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 APPLICATION INFORMATION (continued) DAC8574 I2C Pullup Resistors 1 kΩ to 10 kΩ (typical) Microcontroller or Microprocessor With I2C Port IOVDD 1 VOUTA A3 16 2 VOUTB A2 15 3 VREFH A1 14 4 VDD A0 13 5 VREFL IOVDD 12 6 GND SDA 11 7 VOUTC SCL 10 8 VOUTD LDAC 9 SCL SDA NOTE: DAC8574 power and input/output connections are omitted for clarity, except I C Inputs. Figure 56.
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 APPLICATION INFORMATION (continued) DAC8574 IOVDD 1 VOUTA A3 16 2 VOUTB A2 15 3 VREFH A1 14 4 VDD A0 13 5 VREFL Microcontroller or Microprocessor IOVDD 12 6 GND SDA 11 7 VOUTC SCL 10 8 VOUTD LDAC 9 GPIO-1 GPIO-2 NOTE: DAC8574 power and input/output connections are omitted for clarity, except I C Inputs. Figure 57.
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 APPLICATION INFORMATION (continued) USING REF02 AS A POWER SUPPLY FOR DAC8574 Due to the extremely low supply current required by the DAC8574, a possible configuration is to use a REF02 +5 V precision voltage reference to supply the required voltage to the DAC8574's supply input as well as the reference input, as shown in Figure 58.
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 GENERATING ±5-V, ±10-V, and ± 12-V OUTPUTS FOR PRECISION INDUSTRIAL CONTROL Industrial control applications can require multiple feedback loops consisting of sensors, ADCs, MCUs, DACs, and actuators. Loop accuracy and loop speed are the two important parameters of such control loops. Loop Accuracy: In a control loop, the ADC has to be accurate.
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 Digital Correction of DAC Errors For open-loop applications requiring improved accuracy, offset and gain errors of the DAC8574 can be measured and digitally corrected. To avoid waveform clipping, it is recommended to make the offset and gain error measurements at codes 1024 and 64512 respectively.
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 Table 9.
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 EXAMPLE 4: WRITE 4/4 SCALE TO CHANNEL D ADDRESS [7...0] START 1001 1000 C [7...0] ACK 0001 0110 M [7...0] ACK 1111 1111 L [7...0] ACK 1111 1111 Previous VoutD output voltage is valid ACK STOP VoutB = 5.0 V EXAMPLE 5: Power-Down Channel A, With Hi-Z Output ADDRESS [7...0] START 1001 1000 C [7...0] ACK 0001 0001 M [7...0] ACK 0000 0000 L [7...
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 EXAMPLE 11: Simultaneous Update of All Channels Write 4/4 Scale, 4/3 Scale, 2/4 Scale, and 1/4 Scale Data to Temporary Registers of Channels A, B, C, D Serially, and Update all DACs Simultaneously ADDRESS [7...0] START 1001 1000 C [7...0] ACK 0000 0000 M [7...0] L [7...
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DAC8574 www.ti.com SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004 EXAMPLE 14: Broadcast update command. All channels of all DAC8574s update with previously stored temporary register data. ADDRESS [7...0] START 1001 0000 C [7...0] ACK M [7...0] 0011 0000 ACK XXXX XXXX L [7...0] ACK XXXX XXXX Previous DAC output voltages are valid for all channels, all DAC8574s ACK STOP New data is valid EXAMPLE 15: Broadcast Data. All channels of all DAC8574s get set to code 7. START ADDRESS [7...0] C [7..
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DAC8574 www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DAC8574IPWR Package Package Pins Type Drawing TSSOP PW 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 12.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC8574IPWR TSSOP PW 16 2000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.