Datasheet

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0
500
1000
1500
2000
2500
0 40 80 120 160 200 240 280
I
DD
- Supply Current - µA
f - Frequency
I
REF
Included
V
DD
= 2.7 V
V
DD
= 5.5 V
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0 1 2 3 4 5
Logic Input Voltage - V
I
DD
- Supply Current - mA
T
A
= 25°C, A0 Input (All Other Inputs = GND)
Reference Current Included
V
DD
= V
REF
= 2.7 V
V
DD
= V
REF
= 5.5 V
t - Time - 5µs/div
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
V
OUT
- Output Voltage - V
2.3
2.35
2.4
2.45
2.5
0
5 10 15 20 25 30
V
O
(V, 50 mV/div)
t - Time - µS
V
ref
= V
DD
- 50 mV
Code 7FFFh to 8000h
(Glitch Occurs Every N x 4096
Code Boundary)
0
1
2
3
4
5
6
t – Time – 12µs/div, Fast–Settling Mode
V
OUT
– Output Voltage – V
V
DD
= V
REF
= 5 V
Output
Loaded With
2 kΩ and
200 pF to
GND
-0.005
-0.004
-0.003
-0.002
-0.001
0
0.001
0.002
0.003
0.004
0.005
0 10000 20000 30000 40000 50000 60000
Digital Input Code
Total Unadjusted Error - V
V
DD
= 5 V
DAC8571
SLAS373A – DECEMBER 2002 – REVISED JULY 2003
TYPICAL CHARACTERISTICS (continued)
At T
A
= +25 °C, unless otherwise noted.
SUPPLY CURRENT vs LOGIC INPUT VOLTAGE HISTOGRAM OF CURRENT CONSUMPTION
Figure 13. Figure 14.
EXITING POWER-DOWN MODE OUTPUT GLITCH (Mid-Scale)
Figure 15. Figure 16.
ABSOLUTE ERROR FULL-SCALE SETTLING TIME (Large Signal)
Figure 17. Figure 18.
8