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Not Acknowledge
Acknowledge
1 2 8 9
Clock Pulse for
Acknowledgement
S
START
Condition
Data Output
by Transmitter
Data Output
by Receiver
SCL From
Master
Recognize START or
REPEATED START
Condition
Recognize STOP or
REPEATED START
Condition
Generate ACKNOWLEDGE
Signal
Acknowledgement
Signal From Slave
SDA
SCL
MSB
P
Sr
Sr
or
P
S
or
Sr
START or
Repeated START
Condition
STOP or
Repeated START
Condition
Clock Line Held Low While
Interrupts are Serviced
1 2 7 8 9
ACK
1 2 3 - 8 9
ACK
Address
R/W
DAC8571
SLAS373A – DECEMBER 2002 – REVISED JULY 2003
THEORY OF OPERATION (continued)
Figure 30. Acknowledge on the I
2
C Bus
Figure 31. Bus Protocol
13