Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - DA converter (DAC) VSSOP 8

3 mm x 5 mm

www.ti.com

FEATURES DESCRIPTION

APPLICATIONS

16 Bit DAC

DAC Register

C Block

Power Down

Control Logic

Resistor

Network

Ref +

REF

SDA

SCL

GND

(SENSE)

OUT

Temporary Register

DAC8571

SLAS373A – DECEMBER 2002 – REVISED JULY 2003

16-BIT, LOW POWER, VOLTAGE OUTPUT, I

C INTERFACE DIGITAL-TO-ANALOG

CONVERTER

• Micropower Operation: 160 µA @ 5 V

The DAC8571 is a small low-power, 16-bit voltage

• Power-On Reset to Zero

output DAC with an I

C compatible two-wire serial

interface. Its on-chip precision output amplifier allows

• Single Supply: +2.7 V to +5.5 V

rail-to-rail output swing and settles within 10

• 16-Bit Monotonic

microseconds. The DAC8571 architecture is 16-bit

• Settling Time: 10 µs to ±0.003% FSR

monotonic, and factory trimming typically achieves ±4

• I

C™ Interface With High-Speed Mode

mV absolute accuracy at all codes. The DAC8571

• Supports Data Receive and Transmit

requires an external reference voltage to set its

output voltage range.

• On-Chip Rail-to-Rail Output Buffer

• Double-Buffered Input Register

The low power consumption and small size of this

part make it ideally suited to portable battery

• Supports Synchronous Multichannel Update

operated equipment. The power consumption is typi-

• Offset Error: ±1 mV max at 25 °C

cally 800 µW at V

= 5 V reducing to 1 µW in

• Full-Scale Error: ±3 mV max at 25 °C

power-down mode.

• Small 8 Lead MSOP Package

The DAC8571 incorporates a 2-wire I

C interface.

Standard, fast, and high-speed modes of I

C oper-

ation are all supported up to 3.4 MHz serial clock

• Process Control

speeds. Multichannel synchronous data update and

• Data Acquisition Systems

power-down operations are supported through the I

bus. DAC8571 is also capable of transmitting the

• Closed-Loop Servo Control

contents of its serial shift register, a key feature for

• PC Peripherals

C system verification.

• Portable Instrumentation

The DAC8571 is available in an 8-lead MSOP pack-

age and is specified over -40 °C to 105 °C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

C is a trademark of Philips Corporation.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (32 pages)

PAGE 1
3 mm x 5 mm DAC8571 www.ti.com SLAS373A – DECEMBER 2002 – REVISED JULY 2003 2 16-BIT, LOW POWER, VOLTAGE OUTPUT, I C INTERFACE DIGITAL-TO-ANALOG CONVERTER FEATURES • • • • • • • • • • • • • DESCRIPTION Micropower Operation: 160 µA @ 5 V Power-On Reset to Zero Single Supply: +2.7 V to +5.5 V 16-Bit Monotonic Settling Time: 10 µs to ±0.
PAGE 2
DAC8571 www.ti.com SLAS373A – DECEMBER 2002 – REVISED JULY 2003 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
PAGE 3
DAC8571 www.ti.com SLAS373A – DECEMBER 2002 – REVISED JULY 2003 ELECTRICAL CHARACTERISTICS VDD = +2.7 V to +5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; low power mode; all specifications -40°C to 105°C (unless otherwise noted) DAC8571 PARAMETER CONDITIONS STATIC PERFORMANCE MIN TYP MAX UNITS (1) Resolution 16 Bits ±0.098 Relative accuracy ±1 LSB Measured at code 485, 25°C 0.3 ±1.0 mV Measured at code 485, -40°C...105°C 1.0 ±5.0 Measured at code 64714, 25°C 0.5 ±3.
PAGE 4
DAC8571 www.ti.com SLAS373A – DECEMBER 2002 – REVISED JULY 2003 ELECTRICAL CHARACTERISTICS (continued) VDD = +2.7 V to +5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; low power mode; all specifications -40°C to 105°C (unless otherwise noted) DAC8571 PARAMETER CONDITIONS TYP MAX UNITS VDD = +4.5 V to +5.5 V VIH = VDD, VIL = GND, fast settling 250 400 µA VIH = VDD, VIL = GND, low power 160 225 VIH = VDD, VIL = GND, fast settling 240 380 VIH = VDD, VIL = GND, low power 140 200 VDD = +2.
PAGE 5
DAC8571 www.ti.com SLAS373A – DECEMBER 2002 – REVISED JULY 2003 TIMING CHARACTERISTICS (continued) VDD = +2.7 V to +5.5 V; RL = 2 kΩ to GND; all specifications -40°C to 105°C (unless otherwise noted) SYMBOL tRCL1 tFCL tRCA tFDA tSU; tSTO CB PARAMETER Rise time of SCL signal after a repeated START condition, and after an acknowledge BIT Fall time of SCL signal Rise time of SDA signal Fall time of SDA signal Setup time for STOP condition MAX UNITS Standard mode 20 + 0.
PAGE 6
DAC8571 www.ti.com SLAS373A – DECEMBER 2002 – REVISED JULY 2003 TYPICAL CHARACTERISTICS At TA = +25°C, unless otherwise noted. DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR vs DIGITAL INPUT CODE 1 64 0.8 48 0.4 16 0.2 0 DLE - LSB Linearity Error - LSB 0.6 32 -16 -32 0 - 0.2 - 0.4 - 0.6 -48 - 0.8 -64 -1 0 10000 20000 30000 40000 50000 60000 0 Figure 1. Figure 2.
PAGE 7
DAC8571 www.ti.com SLAS373A – DECEMBER 2002 – REVISED JULY 2003 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. SINK CURRENT AT NEGATIVE RAIL SOURCE CURRENT AT POSITIVE RAIL 5 0.125 VOUT - Output Voltage - V VOUT - Output Voltage - V 0.15 VDD = 2.7 V 0.1 VDD = 5 V 0.075 0.05 VREF = VDD - 10 mV DAC Loaded With 0000 H 0.025 4.95 4.9 VREF = VDD - 10 mV DAC Loaded With FFFFH VDD = 5 V 4.85 0 4.8 0 1 2 3 4 5 0 1 2 Figure 7.
PAGE 8
DAC8571 www.ti.com SLAS373A – DECEMBER 2002 – REVISED JULY 2003 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. SUPPLY CURRENT vs LOGIC INPUT VOLTAGE HISTOGRAM OF CURRENT CONSUMPTION 1 2500 TA = 25°C, A0 Input (All Other Inputs = GND) Reference Current Included IREF Included 2000 0.8 0.7 VDD = VREF = 5.5 V 0.6 VDD = VREF = 2.7 V 0.5 0.4 VDD = 5.5 V VDD = 2.7 V f - Frequency IDD - Supply Current - mA 0.9 1500 1000 0.3 500 0.2 0.
PAGE 9
DAC8571 www.ti.com SLAS373A – DECEMBER 2002 – REVISED JULY 2003 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. HALF-SCALE SETTLING TIME (Large Signal) FULL-SCALE SETTLING TIME (Large Signal) 3.5 2.5 2.0 VDD = VREF =5V Output Loaded With 2 kΩ and 200 pF to GND 1.5 1.0 0.5 3.0 VOUT – Output Voltage – V VOUT – Output Voltage – V 3.0 2.5 2.0 VDD = VREF = 2.7 V Output Loaded With 2 kΩ and 200 pF to GND 1.5 1.0 0.5 0.0 0.
PAGE 10
DAC8571 www.ti.com SLAS373A – DECEMBER 2002 – REVISED JULY 2003 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. Small-Signal Settling Time 5mV/div Trigger Signal Time (2µs/div) Figure 25. 10 FULL-SCALE SETTLING TIME (Small-Signal-Negative Going Step) Output Voltage Output Voltage FULL-SCALE SETTLING TIME (Small-Signal-Positive Going Step) Small-Signal Settling Time 5mV/div Trigger Signal Time (2µs/div) Figure 26.
PAGE 11
DAC8571 www.ti.com SLAS373A – DECEMBER 2002 – REVISED JULY 2003 THEORY OF OPERATION D/A SECTION The architecture of the DAC8571 consists of a string DAC followed by an output buffer amplifier. Figure 27 shows a block diagram of the DAC architecture. Reference Voltage V(SENSE) DAC Register Ref+ Resistor String Ref- _ + VOUT GND Figure 27.
PAGE 12
DAC8571 www.ti.com SLAS373A – DECEMBER 2002 – REVISED JULY 2003 THEORY OF OPERATION (continued) Output Amplifier The output buffer is a gain-of-2 noninverting amplifier capable of generating rail-to-rail voltages at its output, which gives an output range of 0 V to VDD. It is capable of driving a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink capabilities (fast settling) of the output amplifier can be seen in the typical curves.
PAGE 13
DAC8571 www.ti.com SLAS373A – DECEMBER 2002 – REVISED JULY 2003 THEORY OF OPERATION (continued) Data Output by Transmitter Not Acknowledge Data Output by Receiver Acknowledge SCL From Master 1 2 8 9 S Clock Pulse for Acknowledgement START Condition Figure 30.
PAGE 14
DAC8571 SLAS373A – DECEMBER 2002 – REVISED JULY 2003 www.ti.com Master Writing to a Slave Receiver (Standard/Fast Modes) I2C protocol starts when the bus is idle, that is, when SDA and SCL lines are stable high. The master then pulls the SDA line low while SCL is still high indicating that serial data transfer has started. This is called a start condition, and can only be asserted by the master.
PAGE 15
DAC8571 www.ti.com SLAS373A – DECEMBER 2002 – REVISED JULY 2003 Table 1.
PAGE 16
DAC8571 www.ti.com SLAS373A – DECEMBER 2002 – REVISED JULY 2003 Master Reading From a Slave Transmitter (Standard/Fast Modes) I2C protocol starts when the bus is idle, that is, when SDA and SCL lines are stable high. The master then pulls the SDA line low while SCL is still high indicating that serial data transfer has started. This is called a start condition, and can only be asserted by the master.
PAGE 17
DAC8571 www.ti.com SLAS373A – DECEMBER 2002 – REVISED JULY 2003 th master generates a 9 SCL pulse and monitors the state of the SDA line during the high period of this 9th clock cycle (master leaves the SDA line high). The SDA line being pulled low by the receiver during the high period of 9th clock cycle is called an acknowledge signal. If the master receives an acknowledge signal, it knows that a DAC8571 successfully matched the address the master sent.
PAGE 18
DAC8571 www.ti.com SLAS373A – DECEMBER 2002 – REVISED JULY 2003 Master Receiver Reading From a Slave Transmitter (High-Speed Mode) I2C protocol starts when the bus is idle, that is, when SDA and SCL lines are stable high. The master then pulls the SDA line low while SCL is still high indicating that serial data transfer has started. This is called a start condition, and can only be asserted by the master. After the start condition, the master device puts out the high-speed master code 0000 1xxx.
PAGE 19
DAC8571 www.ti.com SLAS373A – DECEMBER 2002 – REVISED JULY 2003 DAC8571 Update Sequence DAC8571 requires a start condition, a valid I2C address, a control byte, an MS byte and an LS byte for an update. The control byte sets the operational mode of the DAC8571. After the receipt of the control byte, DAC8571 expects an MS byte and an LS byte. After the receipt of each byte, DAC8571 acknowledges by pulling the SDA line low.
PAGE 20
DAC8571 www.ti.com SLAS373A – DECEMBER 2002 – REVISED JULY 2003 • C<5>=1, C<4>=0: Update with previously stored data. The contents of MS byte and LS byte data (or power-down information) are ignored. The DAC is updated with the contents of the data previously stored in the temporary register. This mode changes the DAC output. C<5>=1, C<4>=1: Broadcast update, If C<2>=0, DAC is updated with the contents of its temporary register. If C<2>=1, DAC is updated with I2C MS byte and LS byte data.
PAGE 21
DAC8571 www.ti.com SLAS373A – DECEMBER 2002 – REVISED JULY 2003 C<5> C<4> C<2> 0 1 0 MS and LS bytes represent temporary and DAC register data 1 0 0 MS and LS bytes represent I2C data that is discarded 1 1 0 MS and LS bytes represent I2C data that is discarded 1 1 1 MS and LS bytes represent temporary and DAC register data EXAMPLES (A0 TIED TO GND, VDD = 5 V) EXAMPLE 1: Write 1/4 scale to DAC8571 ADDRESS <7...0> START 1001 1000 C<7...0> ACK 0001 0000 M<7...0> ACK 0100 0000 L<7...
PAGE 22
DAC8571 www.ti.com SLAS373A – DECEMBER 2002 – REVISED JULY 2003 EXAMPLE 11: Read back DAC8571 internal data. V denotes valid logic. ADDRESS<7...0> START 1001 1001 ACK M<7...0> MASTER L<7...0> MASTER VVVV VVVV ACK VVVV VVVV ACK C<7...0> MASTER VVVV VVVV NOT ACK STOP EXAMPLE 12: Ramp generation in high speed mode (up to code 7 is shown) HS Master Code START 0000 1000 ADDRESS NOT ACK REPEATED START 1001 1000 C<7...0> ACK 0001 0000 ACK Previous Vout voltage valid MSB<7...0> LSB<7...
PAGE 23
DAC8571 www.ti.com SLAS373A – DECEMBER 2002 – REVISED JULY 2003 After power-up, the device works in low power mode with its normal power consumption of 170 µA at 5 V. At fast settling mode, device consumes 250 µA nominally, but settles in 10 µs. For the three power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not only does the supply current fall but the output stage is also internally switched from the output of the amplifier to a resistor network of known values.
PAGE 24
DAC8571 www.ti.com SLAS373A – DECEMBER 2002 – REVISED JULY 2003 OUTPUT VOLTAGE STABILITY The DAC8571 exhibits excellent temperature stability of 5 ppm/°C typical output voltage drift over the specified temperature range of the device. This enables the output voltage of each channel to stay within a ±25 µV window for a ±1°C ambient temperature change. Good power supply rejection ratio (PSRR) performance reduces supply noise present on VDD from appearing at the outputs to well below 10 µV.
PAGE 25
DAC8571 www.ti.com SLAS373A – DECEMBER 2002 – REVISED JULY 2003 As with the GND connection, VDD is connected to a +5-V power supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point. In addition, the 1-µF to 10-µF, and 0.1-µF bypass capacitors are strongly recommended.
PAGE 26
PACKAGE OPTION ADDENDUM www.ti.
PAGE 27
PACKAGE OPTION ADDENDUM www.ti.
PAGE 28
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DAC8571IDGKR Package Package Pins Type Drawing VSSOP DGK 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 5.3 B0 (mm) K0 (mm) P1 (mm) 3.4 1.4 8.0 W Pin1 (mm) Quadrant 12.
PAGE 29
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC8571IDGKR VSSOP DGK 8 2500 367.0 367.0 35.
PAGE 30
PAGE 31
PAGE 32
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.