Datasheet
1
2
3
4
5
6
7
14
13
12
11
10
9
SCLK
D
IN
GND
V B
OUT
V D
OUT
V F
OUT
V H
OUT
SYNC
AV
DD
V A
OUT
V C
OUT
V E
OUT
V G
OUT
V IN/V OUT
REF REF
DAC7568
DAC8168
8
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SCLK
D
IN
GND
V B
OUT
V D
OUT
V F
OUT
V H
OUT
CLR
LDAC
SYNC
AV
DD
V A
OUT
V C
OUT
V E
OUT
V G
OUT
V IN/V OUT
REF REF
DAC7568
DAC8168
DAC8568
DAC7568
DAC8168
DAC8568
SBAS430D –JANUARY 2009–REVISED MAY 2012
www.ti.com
PIN CONFIGURATIONS
PW PACKAGE
PW PACKAGE
TSSOP-16
TSSOP-14
(TOP VIEW)
(TOP VIEW)
PIN DESCRIPTIONS
16-PIN 14-PIN NAME DESCRIPTION
1 — LDAC Load DACs.
Level-triggered control input (active low). This input is the frame synchronization signal for the input
data. When SYNC goes low, it enables the input shift register, and data are sampled on subsequent
2 1 SYNC falling clock edges. The DAC output updates following the 32nd clock. If SYNC is taken high before
the 31st clock edge, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored
by the DAC7568/DAC8168/DAC8568. Schmitt-Trigger logic input.
3 2 AV
DD
Power-supply input, 2.7V to 5.5V
4 3 V
OUT
A Analog output voltage from DAC A
5 4 V
OUT
C Analog output voltage from DAC C
6 5 V
OUT
E Analog output voltage from DAC E
7 6 V
OUT
G Analog output voltage from DAC G
V
REF
IN/
8 7 Positive reference input / reference output 2.5V if internal reference used.
(1)
V
REF
OUT
9 — CLR Asynchronous clear input.
10 8 V
OUT
H Analog output voltage from DAC H
11 9 V
OUT
F Analog output voltage from DAC F
12 10 V
OUT
D Analog output voltage from DAC D
13 11 V
OUT
B Analog output voltage from DAC B
14 12 GND Ground reference point for all circuitry on the device
Serial data input. Data are clocked into the 32-bit input shift register on each falling edge of the serial
15 13 D
IN
clock input. Schmitt-Trigger logic input.
16 14 SCLK Serial clock input. Data can be transferred at rates up to 50MHz. Schmitt-Trigger logic input.
(1) Grades A and B, external V
REF
IN (max) ≤ AV
DD
; grades C and D, external V
REF
IN (max) ≤ AV
DD
/2.
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