Datasheet

SYNC
SCLK
D
IN
Microwireä
CS
SK
SO
DAC8568
(1)
NOTE:(1)AlsoappliestoDAC7568andDAC8168.Additionalpinsomittedforclarity.
PC7
SCK
MOSI
SYNC
DAC8568
(1)
SCLK
D
IN
NOTE:(1)AlsoappliestoDAC7568andDAC8168.Additionalpinsomittedforclarity.
68HC11
(1)
P3.3
TXD
RXD
SYNC
SCLK
D
IN
80C51/80L51
(1)
DAC8568
(1)
NOTE:(1)AlsoappliestoDAC7568andDAC8168.Additionalpinsomittedforclarity.
DAC7568
DAC8168
DAC8568
www.ti.com SBAS430D –JANUARY 2009–REVISED MAY 2012
MICROPROCESSOR INTERFACING
DAC7568/DAC8168/DAC8568 to an 8051 Interface
Figure 129 shows a serial interface between the
DAC7568, DAC8168, and DAC8568 and a typical
8051-type microcontroller. The setup for the interface
is as follows: TXD of the 8051 drives SCLK of the
DAC7568, DAC8168, or DAC8568, while RXD drives
Figure 130. DAC7568/DAC8168/DAC8568 to
the serial data line of the device. The SYNC signal is
Microwire Interface
derived from a bit-programmable pin on the port of
the 8051; in this case, port line P3.3 is used. When
DAC7568/DAC8168/DAC8568 to 68HC11 Interface
data are to be transmitted to the DAC7568,
DAC8168, and DAC8568, P3.3 is taken low. The
Figure 131 shows a serial interface between the
8051 transmits data in 8-bit bytes; thus, only eight
DAC7568/DAC8168/DAC8568 and the 68HC11
falling clock edges occur in the transmit cycle. To
microcontroller. SCK of the 68HC11 drives the SCLK
load data to the DAC, P3.3 is left low after the first
of the DAC7568, DAC8168, and DAC8568, while the
eight bits are transmitted; then, a second write cycle
MOSI output drives the serial data line of the DAC.
is initiated to transmit the second byte of data. P3.3 is
The SYNC signal derives from a port line (PC7),
taken high following the completion of the third write
similar to the 8051 diagram.
cycle. The 8051 outputs the serial data in a format
that has the LSB first. The DAC7568, DAC8168, and
DAC8568 require the data with the MSB as the first
bit received. Therefore, the 8051 transmit routine
must take this requirement into account, and mirror
the data as needed.
Figure 131. DAC7568/DAC8168/DAC8568 to
68HC11 Interface
The 68HC11 should be configured so that its CPOL
bit is '0' and its CPHA bit is '1'. This configuration
causes data appearing on the MOSI output to be
Figure 129. DAC7568/DAC8168/DAC8568 to
valid on the falling edge of SCK. When data are
80C51/80L51 Interface
being transmitted to the DAC, the SYNC line is held
low (PC7). Serial data from the 68HC11 are
DAC7568/DAC8168/DAC8568 to Microwire
transmitted in 8-bit bytes with only eight falling clock
Interface
edges occurring in the transmit cycle. (Data are
transmitted MSB first.) In order to load data to the
Figure 130 shows an interface between the
DAC7568, DAC8168, and DAC8568, PC7 is left low
DAC7568, DAC8168, and DAC8568 and any
after the first eight bits are transferred; then, a second
Microwire-compatible device. Serial data are shifted
and third serial write operation are performed to the
out on the falling edge of the serial clock and are
DAC. PC7 is taken high at the end of this procedure.
clocked into the DAC7568, DAC8168, and DAC8568
on the rising edge of the SK signal.
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