Datasheet

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DAC7568

DAC8168

DAC8568

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SBAS430D –JANUARY 2009–REVISED MAY 2012

CLEAR CODE REGISTER and CLR PIN sequence, this write sequence is aborted and the

DAC registers and DAC buffers are cleared as

The DAC7568, DAC8168, and DAC8568 contain a

described previously.

clear code register. The clear code register can be

accessed via the serial peripheral interface (SPI) and When performing a software reset of the device, the

is user-configurable. Bringing the CLR pin low clears clear code register is set back to its default mode

the content of all DAC registers and all DAC buffers, (DB1 = DB0 = '0'). Setting the clear code register to

and replaces the code with the code determined by DB1 = DB0 = '1' ignores any activity on the external

the clear code register. The clear code register can CLR pin.

be written to by applying the commands showed in

Table 13. The control bits must be set as follows to

SOFTWARE RESET FUNCTION

access the clear code register that is programmed via

The DAC7568, DAC8168, and DAC8568 contain a

the feature bits, F0 and F1: C3 = '0', C2 = '1', C1 =

software reset feature. If the software reset feature is

'0', and C0 = '1'. The default setting of the clear code

executed, all registers inside the device are reset to

default settings; that is, all DAC channels are reset to

when CLR pin is brought low. The CLR pin is falling-

the power-on reset code (power on reset to zero

edge triggered; therefore, the device exits clear code

scale for grades A and C; power on reset to midscale

mode on the 32nd falling edge of the next write

for grades B and D).

sequence. If CLR pin is brought low during a write

Table 13. Clear Code Register

DB30- DB19-

DB31

DB28

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DESCRIPTION

Don't D16-

0 Care C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 F3 F2 F1 F0 GENERAL DATA FORMAT

Clear all DAC outputs to zero scale (default

0 X 0 1 0 1 X X X X X X X X X X X X X 0 0

mode)

0 X 0 1 0 1 X X X X X X X X X X X X X 0 1 Clear all DAC outputs to midscale

0 X 0 1 0 1 X X X X X X X X X X X X X 1 0 Clear all DAC outputs to full-scale

0 X 0 1 0 1 X X X X X X X X X X X X X 1 1 Ignore external CLR pin

Table 14. Software Reset