Datasheet

CLK
SYNC
D
IN
ValidWriteSequence:
Output/ModeUpdates onthe32ndFallingEdge
31stFallingEdge 32ndFallingEdge
DB31
DB0
DB31
DB0
Invalid/InterruptedWriteSequence:
Output/ModeDoesNotUpdate onthe32ndFallingEdge
DAC7568
DAC8168
DAC8568
www.ti.com SBAS430D –JANUARY 2009–REVISED MAY 2012
SYNC INTERRUPT In synchronous mode, data are updated with the
falling edge of the 32nd SCLK cycle, which follows a
In a normal write sequence, the SYNC line stays low
falling edge of SYNC. For such synchronous updates,
for at least 32 falling edges of SCLK and the
the LDAC pin is not required and it must be
addressed DAC register updates on the 32nd falling
connected to GND permanently.
edge. However, if SYNC is brought high before the
31st falling edge, it acts as an interrupt to the write In asynchronous mode, the LDAC pin is used as a
sequence; the shift register resets and the write negative edge triggered timing signal for
sequence is discarded. Neither an update of the data simultaneous DAC updates. Multiple single-channel
buffer contents, DAC register contents, nor a change updates can be done in order to set different channel
in the operating mode occurs (as shown in buffers to desired values and then make a falling
Figure 123). edge on LDAC pin to simultaneously update the DAC
output registers. Data buffers of all channels must be
loaded with desired data before an LDAC falling
POWER-ON RESET TO ZERO SCALE OR
edge. After a high-to-low LDAC transition, all DACs
MIDSCALE
are simultaneously updated with the last contents of
The DAC7568, DAC8168, and DAC8568 contain a
the corresponding data buffers. If the content of a
power-on reset circuit that controls the output voltage
data buffer is not changed, the corresponding DAC
during power-up. For device grades A and C on
output remains unchanged after the LDAC pin is
power-up, all DAC registers are filled with zeros and
triggered.
the output voltages of all DAC channels are set to
Alternatively, all DAC outputs can be updated
zero scale. For device grades B and D all DAC
simultaneously using the built-in software function of
registers are set to have all DAC channels power up
LDAC. The LDAC register offers additional flexibility
in midscale. All DAC channels remain that way until a
and control by allowing the selection of which DAC
valid write sequence and load command are made to
channel(s) should be updated simultaneously when
the respective DAC channel. The power-on reset is
the LDAC pin is being brought low. The LDAC
useful in applications where it is important to know
register is loaded with an 8-bit word (DB0 to DB7)
the state of the output of each DAC while the device
using control bits C3, C2, C1, and C0 (see Table 11).
is in the process of powering up. No device pin
The default value for each bit, and therefore for each
should be brought high before power is applied to the
DAC channel, is zero. The external LDAC pin
device. The internal reference is powered off / down
operates in normal mode. If the LDAC register bit is
by default and remains that way until a valid
set to '1', it overrides the LDAC pin (the LDAC pin is
reference-change command is executed.
internally tied low for that particular DAC channel)
and this DAC channel updates synchronously after
LDAC FUNCTIONALITY
the falling edge of the 32nd SCLK cycle. However, if
The DAC7568, DAC8168, and DAC8568 offer both a
the LDAC register bit is set to '0', the DAC channel is
software and hardware simultaneous update and
controlled by the LDAC pin.
control function. The DAC double-buffered
The combination of software and hardware
architecture has been designed so that new data can
simultaneous update functions is particularly useful in
be entered for each DAC without disturbing the
applications when updating only selective DAC
analog outputs.
channels simultaneously, while keeping the other
DAC7568, DAC8168, and DAC8568 data updates
channels unaffected and updating those channels
can be performed either in synchronous or in
synchronously; see Table 11 for more information.
asynchronous mode.
Figure 123. SYNC Interrupt Facility
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