Datasheet

DAC7568
DAC8168
DAC8568
SBAS430D –JANUARY 2009–REVISED MAY 2012 www.ti.com
SERIAL INTERFACE The data format is straight binary with all '0's
corresponding to 0V output and all '1's corresponding
The DAC7568, DAC8168, and DAC8568 have a 3-
to full-scale output. For all documentation purposes,
wire serial interface (SYNC, SCLK, and D
IN
; see the
the data format and representation used here is a
Pin Configurations) compatible with SPI, QSPI, and
true 16-bit pattern (that is, FFFFh for data word for
Microwire interface standards, as well as most DSPs.
full-scale) that the DAC7568, DAC8168, and
See the Serial Write Operation timing diagram
DAC8568 require.
(Figure 1) for an example of a typical write sequence.
The write sequence begins by bringing the SYNC line
The DAC7568, DAC8168, and DAC8568 input shift
low. Data from the D
IN
line are clocked into the 32-bit
register is 32-bits wide, consisting of four prefix bits
shift register on each falling edge of SCLK. The serial
(DB31 to DB28), four control bits (DB27 to DB24), 16
clock frequency can be as high as 50MHz, making
data bits (DB23 to DB4), and four feature bits. The 16
the DAC7568, DAC8168, and DAC8568 compatible
data bits comprise the 16-, 14-, or 12-bit input code.
with high-speed DSPs. On the 32nd falling edge of
When writing to the DAC register (data transfer), bits
the serial clock, the last data bit is clocked into the
DB0 to DB3 (for 16-bit operation), DB0 to DB5 (for
shift register and the shift register locks. Further
14-bit operation), and DB0 to DB7 (for 12-bit
clocking does not change the shift register data. After
operation) are ignored by the DAC and should be
receiving the 32nd falling clock edge, the DAC7568,
treated as don't care bits (see Table 8 to Table 10).
DAC8168, and DAC8568 decode the four control bits
All 32 bits of data are loaded into the DAC under the
and four address bits and 16/14/12 data bits to
control of the serial clock input, SCLK.
perform the required function, without waiting for a
SYNC rising edge. A new write sequence starts at the
DB31 (MSB) is the first bit that is loaded into the DAC
next falling edge of SYNC. A rising edge of SYNC
shift register and must be always set to '0'. It is
before the 31st-bit sequence is complete resets the
followed by the rest of the 32-bit word pattern, left-
SPI interface; no data transfer occurs. After the 32nd
aligned. This configuration means that the first 32 bits
falling edge of SCLK is received, the SYNC line may
of data are latched into the shift register and any
be kept low or brought high. In either case, the
further clocking of data is ignored. When the DAC
minimum delay time from the 32nd falling SCLK edge
registers are being written to, the DAC7568,
to the next falling SYNC edge must be met in order to
DAC8168, and DAC8568 receive all 32 bits of data,
properly begin the next cycle; see the Serial Write
ignore DB31 to DB28, and decode the second set of
Operation timing diagram (Figure 1). To assure the
four bits (DB27 to DB24) in order to determine the
lowest power consumption of the device, care should
DAC operating/control mode (see Table 11). Bits
be taken that the levels are as close to each rail as
DB23 to DB20 are used to address selected DAC
possible. Refer to the 5.5V, 3.6V, and 2.7V Typical
channels. The next 16/14/12 bits of data that follow
Characteristics sections for the Power-Supply Current
are decoded by the DAC to determine the equivalent
vs Logic Input Voltage graphs (Figure 43, Figure 44,
analog output. The last four data bits (DB0 to DB3 for
Figure 70, Figure 72, Figure 102, and Figure 103).
DAC8568), last data six bits (DB0 to DB5 for
DAC8168), or last eight data bits (DB0 to DB7 for
DAC7568) are ignored in this case. For more details
on these and other commands (such as write to
LDAC register, power down DACs, etc.), see
Table 11.
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