Datasheet

DAC8562, DAC8563
DAC8162, DAC8163
DAC7562, DAC7563
SLAS719D –AUGUST 2010–REVISED AUGUST 2012 www.ti.com
Input Shift Register
The input shift register (SR) of the DAC856x, DAC816x, and DAC756x is 24 bits wide (as shown in Table 8,
Table 9, and Table 10, respectively), and consists of two don’t care bits (DB23 to DB22), three command bits
(DB21 to DB19), three address bits (DB18 to DB16), and 16 data bits (DB15 to DB0). The 16 data bits comprise
the 16-, 14-, or 12-bit input code.
Table 8. DAC856x Data Input Register Format
Command Address Data
X
(1)
X C2 C1 C0 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DB23 DB0
(1) X' denotes don't care bits.
Table 9. DAC816x Data Input Register Format
Command Address Data
X X C2 C1 C0 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X
DB23 DB0
Table 10. DAC756x Data Input Register Format
Command Address Data
X X C2 C1 C0 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
DB23 DB0
The DAC856x, DAC816x, and DAC756x support a number of different load commands. The load commands are
summarized in Table 11 and Table 12, and fully exhausted in Table 13.
Table 11. Commands for the DAC856x, DAC816x, and DAC756x
C2 C1 C0
Command
(DB21) (DB20) (DB19)
0 0 0 Write to input register n (Table 12)
0 0 1 Software LDAC, update DAC register n (Table 12)
0 1 0 Write to input register n (Table 12) and update all DAC registers
0 1 1 Write to input register n and update DAC register n (Table 12)
1 0 0 Set DAC power up/down mode
1 0 1 Software reset
1 1 0 Set LDAC registers
1 1 1 Enable/disable internal reference
Table 12. Address Select for the DAC856x, DAC816x, and DAC756x
A2 A1 A0
Channel (n)
(DB18) (DB17) (DB16)
0 0 0 DAC-A
0 0 1 DAC-B
0 1 0 Gain (only use with command 000)
0 1 1 Reserved
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 DAC-A and DAC-B
32 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563